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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [doc/] [sch/] [cpu_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1500 300 1 0 0 in_port_vector.sym
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{
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T 1500 300 5 10 1 1 0 6 1 1
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refdes=vec_int[7:0]
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}
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C 1500 700 1 0 0 in_port_vector.sym
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{
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T 1500 700 5 10 1 1 0 6 1 1
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refdes=rdata[15:0]
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}
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C 1500 1100 1 0 0 in_port_vector.sym
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{
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T 1500 1100 5 10 1 1 0 6 1 1
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refdes=pg0_data[7:0]
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}
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C 1500 1500 1 0 0 in_port.sym
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{
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T 1500 1500 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1500 1900 1 0 0 in_port.sym
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{
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T 1500 1900 5 10 1 1 0 6 1 1
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refdes=nmi
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}
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C 1500 2300 1 0 0 in_port.sym
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{
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T 1500 2300 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 1500 2700 1 0 0 in_port.sym
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{
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T 1500 2700 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 4500 300  1 0  0 out_port_vector.sym
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{
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T 5500 300 5  10 1 1 0 0 1 1
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refdes=wdata[7:0]
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}
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C 4500 700  1 0  0 out_port_vector.sym
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{
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T 5500 700 5  10 1 1 0 0 1 1
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refdes=pg0_add[7:0]
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}
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C 4500 1100  1 0  0 out_port_vector.sym
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{
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T 5500 1100 5  10 1 1 0 0 1 1
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refdes=alu_status[7:0]
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}
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C 4500 1500  1 0  0 out_port_vector.sym
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{
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T 5500 1500 5  10 1 1 0 0 1 1
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refdes=addr[CPU_ADD-1:0]
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}
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C 4500 1900  1 0 0 out_port.sym
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{
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T 5500 1900 5  10 1 1 0 0 1 1
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refdes=wr
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}
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C 4500 2300  1 0 0 out_port.sym
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{
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T 5500 2300 5  10 1 1 0 0 1 1
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refdes=rd
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}
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C 4500 2700  1 0 0 out_port.sym
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{
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T 5500 2700 5  10 1 1 0 0 1 1
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refdes=pg0_wr
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}
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C 4500 3100  1 0 0 out_port.sym
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{
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T 5500 3100 5  10 1 1 0 0 1 1
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refdes=pg0_rd
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}

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