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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [doc/] [sch/] [T6502_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 2600 300 1 0 0 in_port_vector.sym
3 
{
4 
T 2600 300 5 10 1 1 0 6 1 1
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refdes=wb_jsp_dat_i[7:0]
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}
7 
C 2600 700 1 0 0 in_port_vector.sym
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{
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T 2600 700 5 10 1 1 0 6 1 1
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refdes=gpio_1_in[7:0]
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}
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C 2600 1100 1 0 0 in_port_vector.sym
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{
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T 2600 1100 5 10 1 1 0 6 1 1
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refdes=gpio_0_in[7:0]
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}
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C 2600 1500 1 0 0 in_port_vector.sym
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{
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T 2600 1500 5 10 1 1 0 6 1 1
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refdes=ext_rdata[15:0]
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}
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C 2600 1900 1 0 0 in_port_vector.sym
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{
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T 2600 1900 5 10 1 1 0 6 1 1
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refdes=ext_irq_in[3:0]
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}
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C 2600 2300 1 0 0 in_port.sym
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{
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T 2600 2300 5 10 1 1 0 6 1 1
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refdes=wb_jsp_stb_i
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}
32 
C 2600 2700 1 0 0 in_port.sym
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{
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T 2600 2700 5 10 1 1 0 6 1 1
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refdes=uart_rxd_pad_in
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}
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C 2600 3100 1 0 0 in_port.sym
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{
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T 2600 3100 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2600 3500 1 0 0 in_port.sym
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{
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T 2600 3500 5 10 1 1 0 6 1 1
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refdes=ps2_data_pad_in
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}
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C 2600 3900 1 0 0 in_port.sym
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{
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T 2600 3900 5 10 1 1 0 6 1 1
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refdes=ps2_clk_pad_in
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}
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C 2600 4300 1 0 0 in_port.sym
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{
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T 2600 4300 5 10 1 1 0 6 1 1
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refdes=jtag_update_dr_clk
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}
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C 2600 4700 1 0 0 in_port.sym
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{
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T 2600 4700 5 10 1 1 0 6 1 1
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refdes=jtag_test_logic_reset
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}
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C 2600 5100 1 0 0 in_port.sym
63 
{
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T 2600 5100 5 10 1 1 0 6 1 1
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refdes=jtag_tdi
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}
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C 2600 5500 1 0 0 in_port.sym
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{
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T 2600 5500 5 10 1 1 0 6 1 1
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refdes=jtag_shiftcapture_dr_clk
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}
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C 2600 5900 1 0 0 in_port.sym
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{
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T 2600 5900 5 10 1 1 0 6 1 1
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refdes=jtag_shift_dr
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}
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C 2600 6300 1 0 0 in_port.sym
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{
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T 2600 6300 5 10 1 1 0 6 1 1
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refdes=jtag_select
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}
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C 2600 6700 1 0 0 in_port.sym
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{
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T 2600 6700 5 10 1 1 0 6 1 1
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refdes=jtag_capture_dr
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}
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C 2600 7100 1 0 0 in_port.sym
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{
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T 2600 7100 5 10 1 1 0 6 1 1
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refdes=ext_wait
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}
92 
C 2600 7500 1 0 0 in_port.sym
93 
{
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T 2600 7500 5 10 1 1 0 6 1 1
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refdes=cts_pad_in
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}
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C 2600 7900 1 0 0 in_port.sym
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{
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T 2600 7900 5 10 1 1 0 6 1 1
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refdes=clk
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}
102 
C 6100 300  1 0  0 out_port_vector.sym
103 
{
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T 7100 300 5  10 1 1 0 0 1 1
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refdes=vga_red_pad_out[2:0]
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}
107 
C 6100 700  1 0  0 out_port_vector.sym
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{
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T 7100 700 5  10 1 1 0 0 1 1
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refdes=vga_green_pad_out[2:0]
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}
112 
C 6100 1100  1 0  0 out_port_vector.sym
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{
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T 7100 1100 5  10 1 1 0 0 1 1
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refdes=vga_blue_pad_out[1:0]
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}
117 
C 6100 1500  1 0  0 out_port_vector.sym
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{
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T 7100 1500 5  10 1 1 0 0 1 1
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refdes=jsp_data_out[7:0]
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}
122 
C 6100 1900  1 0  0 out_port_vector.sym
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{
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T 7100 1900 5  10 1 1 0 0 1 1
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refdes=gpio_1_out[7:0]
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}
127 
C 6100 2300  1 0  0 out_port_vector.sym
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{
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T 7100 2300 5  10 1 1 0 0 1 1
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refdes=gpio_1_oe[7:0]
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}
132 
C 6100 2700  1 0  0 out_port_vector.sym
133 
{
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T 7100 2700 5  10 1 1 0 0 1 1
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refdes=gpio_0_out[7:0]
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}
137 
C 6100 3100  1 0  0 out_port_vector.sym
138 
{
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T 7100 3100 5  10 1 1 0 0 1 1
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refdes=gpio_0_oe[7:0]
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}
142 
C 6100 3500  1 0  0 out_port_vector.sym
143 
{
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T 7100 3500 5  10 1 1 0 0 1 1
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refdes=ext_wdata[15:0]
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}
147 
C 6100 3900  1 0  0 out_port_vector.sym
148 
{
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T 7100 3900 5  10 1 1 0 0 1 1
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refdes=ext_cs[1:0]
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}
152 
C 6100 4300  1 0  0 out_port_vector.sym
153 
{
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T 7100 4300 5  10 1 1 0 0 1 1
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refdes=ext_addr[23:1]
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}
157 
C 6100 4700  1 0  0 out_port_vector.sym
158 
{
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T 7100 4700 5  10 1 1 0 0 1 1
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refdes=alu_status[7:0]
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}
162 
C 6100 5100  1 0 0 out_port.sym
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{
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T 7100 5100 5  10 1 1 0 0 1 1
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refdes=vga_vsync_n_pad_out
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}
167 
C 6100 5500  1 0 0 out_port.sym
168 
{
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T 7100 5500 5  10 1 1 0 0 1 1
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refdes=vga_hsync_n_pad_out
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}
172 
C 6100 5900  1 0 0 out_port.sym
173 
{
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T 7100 5900 5  10 1 1 0 0 1 1
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refdes=uart_txd_pad_out
176 
}
177 
C 6100 6300  1 0 0 out_port.sym
178 
{
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T 7100 6300 5  10 1 1 0 0 1 1
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refdes=rts_pad_out
181 
}
182 
C 6100 6700  1 0 0 out_port.sym
183 
{
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T 7100 6700 5  10 1 1 0 0 1 1
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refdes=ps2_data_pad_oe
186 
}
187 
C 6100 7100  1 0 0 out_port.sym
188 
{
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T 7100 7100 5  10 1 1 0 0 1 1
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refdes=ps2_clk_pad_oe
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}
192 
C 6100 7500  1 0 0 out_port.sym
193 
{
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T 7100 7500 5  10 1 1 0 0 1 1
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refdes=jtag_tdo
196 
}
197 
C 6100 7900  1 0 0 out_port.sym
198 
{
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T 7100 7900 5  10 1 1 0 0 1 1
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refdes=ext_wr
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}
202 
C 6100 8300  1 0 0 out_port.sym
203 
{
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T 7100 8300 5  10 1 1 0 0 1 1
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refdes=ext_ub
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}
207 
C 6100 8700  1 0 0 out_port.sym
208 
{
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T 7100 8700 5  10 1 1 0 0 1 1
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refdes=ext_stb
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}
212 
C 6100 9100  1 0 0 out_port.sym
213 
{
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T 7100 9100 5  10 1 1 0 0 1 1
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refdes=ext_rd
216 
}
217 
C 6100 9500  1 0 0 out_port.sym
218 
{
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T 7100 9500 5  10 1 1 0 0 1 1
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refdes=ext_lb
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}
222 
C 6100 9900  1 0 0 out_port.sym
223 
{
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T 7100 9900 5  10 1 1 0 0 1 1
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refdes=biu_wr_strobe
226 
}

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