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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [doc/] [sym/] [T6502_def.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  5000 5300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 5450   5 10 1 1 0 0 1 1
4 
device=T6502_def
5 
T 400 5650 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 5800    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 5800    0 10 0 1 0 0 1 1
10 
library=Mos6502
11 
T 400 5800    0 10 0 1 0 0 1 1
12 
component=T6502
13 
T 400 5800    0 10 0 1 0 0 1 1
14 
version=def
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=wb_jsp_dat_i[7:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 10 1 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=gpio_1_in[7:0]
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 10 1 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=gpio_0_in[7:0]
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 10 1 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=ext_rdata[15:0]
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 10 1 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=ext_irq_in[3:0]
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=wb_jsp_stb_i
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=uart_rxd_pad_in
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
67 
pinnumber=reset
68 
T 400 1600 5 10 0 1 0 1 1 1
69 
pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
72 
{
73 
T 400 1800 5 10 1 1 0 1 1 1
74 
pinnumber=ps2_data_pad_in
75 
T 400 1800 5 10 0 1 0 1 1 1
76 
pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
79 
{
80 
T 400 2000 5 10 1 1 0 1 1 1
81 
pinnumber=ps2_clk_pad_in
82 
T 400 2000 5 10 0 1 0 1 1 1
83 
pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
86 
{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=jtag_update_dr_clk
89 
T 400 2200 5 10 0 1 0 1 1 1
90 
pinseq=11
91 
}
92 
P 300 2400 0 2400 4 0 1
93 
{
94 
T 400 2400 5 10 1 1 0 1 1 1
95 
pinnumber=jtag_test_logic_reset
96 
T 400 2400 5 10 0 1 0 1 1 1
97 
pinseq=12
98 
}
99 
P 300 2600 0 2600 4 0 1
100 
{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=jtag_tdi
103 
T 400 2600 5 10 0 1 0 1 1 1
104 
pinseq=13
105 
}
106 
P 300 2800 0 2800 4 0 1
107 
{
108 
T 400 2800 5 10 1 1 0 1 1 1
109 
pinnumber=jtag_shiftcapture_dr_clk
110 
T 400 2800 5 10 0 1 0 1 1 1
111 
pinseq=14
112 
}
113 
P 300 3000 0 3000 4 0 1
114 
{
115 
T 400 3000 5 10 1 1 0 1 1 1
116 
pinnumber=jtag_shift_dr
117 
T 400 3000 5 10 0 1 0 1 1 1
118 
pinseq=15
119 
}
120 
P 300 3200 0 3200 4 0 1
121 
{
122 
T 400 3200 5 10 1 1 0 1 1 1
123 
pinnumber=jtag_select
124 
T 400 3200 5 10 0 1 0 1 1 1
125 
pinseq=16
126 
}
127 
P 300 3400 0 3400 4 0 1
128 
{
129 
T 400 3400 5 10 1 1 0 1 1 1
130 
pinnumber=jtag_capture_dr
131 
T 400 3400 5 10 0 1 0 1 1 1
132 
pinseq=17
133 
}
134 
P 300 3600 0 3600 4 0 1
135 
{
136 
T 400 3600 5 10 1 1 0 1 1 1
137 
pinnumber=ext_wait
138 
T 400 3600 5 10 0 1 0 1 1 1
139 
pinseq=18
140 
}
141 
P 300 3800 0 3800 4 0 1
142 
{
143 
T 400 3800 5 10 1 1 0 1 1 1
144 
pinnumber=cts_pad_in
145 
T 400 3800 5 10 0 1 0 1 1 1
146 
pinseq=19
147 
}
148 
P 300 4000 0 4000 4 0 1
149 
{
150 
T 400 4000 5 10 1 1 0 1 1 1
151 
pinnumber=clk
152 
T 400 4000 5 10 0 1 0 1 1 1
153 
pinseq=20
154 
}
155 
P 5300 200 5600 200 10 1 1
156 
{
157 
T 5200 200 5  10 1 1 0 7 1 1
158 
pinnumber=vga_red_pad_out[2:0]
159 
T 5200 200 5  10 0 1 0 7 1 1
160 
pinseq=21
161 
}
162 
P 5300 400 5600 400 10 1 1
163 
{
164 
T 5200 400 5  10 1 1 0 7 1 1
165 
pinnumber=vga_green_pad_out[2:0]
166 
T 5200 400 5  10 0 1 0 7 1 1
167 
pinseq=22
168 
}
169 
P 5300 600 5600 600 10 1 1
170 
{
171 
T 5200 600 5  10 1 1 0 7 1 1
172 
pinnumber=vga_blue_pad_out[1:0]
173 
T 5200 600 5  10 0 1 0 7 1 1
174 
pinseq=23
175 
}
176 
P 5300 800 5600 800 10 1 1
177 
{
178 
T 5200 800 5  10 1 1 0 7 1 1
179 
pinnumber=jsp_data_out[7:0]
180 
T 5200 800 5  10 0 1 0 7 1 1
181 
pinseq=24
182 
}
183 
P 5300 1000 5600 1000 10 1 1
184 
{
185 
T 5200 1000 5  10 1 1 0 7 1 1
186 
pinnumber=gpio_1_out[7:0]
187 
T 5200 1000 5  10 0 1 0 7 1 1
188 
pinseq=25
189 
}
190 
P 5300 1200 5600 1200 10 1 1
191 
{
192 
T 5200 1200 5  10 1 1 0 7 1 1
193 
pinnumber=gpio_1_oe[7:0]
194 
T 5200 1200 5  10 0 1 0 7 1 1
195 
pinseq=26
196 
}
197 
P 5300 1400 5600 1400 10 1 1
198 
{
199 
T 5200 1400 5  10 1 1 0 7 1 1
200 
pinnumber=gpio_0_out[7:0]
201 
T 5200 1400 5  10 0 1 0 7 1 1
202 
pinseq=27
203 
}
204 
P 5300 1600 5600 1600 10 1 1
205 
{
206 
T 5200 1600 5  10 1 1 0 7 1 1
207 
pinnumber=gpio_0_oe[7:0]
208 
T 5200 1600 5  10 0 1 0 7 1 1
209 
pinseq=28
210 
}
211 
P 5300 1800 5600 1800 10 1 1
212 
{
213 
T 5200 1800 5  10 1 1 0 7 1 1
214 
pinnumber=ext_wdata[15:0]
215 
T 5200 1800 5  10 0 1 0 7 1 1
216 
pinseq=29
217 
}
218 
P 5300 2000 5600 2000 10 1 1
219 
{
220 
T 5200 2000 5  10 1 1 0 7 1 1
221 
pinnumber=ext_cs[1:0]
222 
T 5200 2000 5  10 0 1 0 7 1 1
223 
pinseq=30
224 
}
225 
P 5300 2200 5600 2200 10 1 1
226 
{
227 
T 5200 2200 5  10 1 1 0 7 1 1
228 
pinnumber=ext_addr[23:1]
229 
T 5200 2200 5  10 0 1 0 7 1 1
230 
pinseq=31
231 
}
232 
P 5300 2400 5600 2400 10 1 1
233 
{
234 
T 5200 2400 5  10 1 1 0 7 1 1
235 
pinnumber=alu_status[7:0]
236 
T 5200 2400 5  10 0 1 0 7 1 1
237 
pinseq=32
238 
}
239 
P 5300 2600 5600 2600 4 0 1
240 
{
241 
T 5200 2600 5  10 1 1 0 7 1 1
242 
pinnumber=vga_vsync_n_pad_out
243 
T 5300 2600 5  10 0 1 0 7 1 1
244 
pinseq=33
245 
}
246 
P 5300 2800 5600 2800 4 0 1
247 
{
248 
T 5200 2800 5  10 1 1 0 7 1 1
249 
pinnumber=vga_hsync_n_pad_out
250 
T 5300 2800 5  10 0 1 0 7 1 1
251 
pinseq=34
252 
}
253 
P 5300 3000 5600 3000 4 0 1
254 
{
255 
T 5200 3000 5  10 1 1 0 7 1 1
256 
pinnumber=uart_txd_pad_out
257 
T 5300 3000 5  10 0 1 0 7 1 1
258 
pinseq=35
259 
}
260 
P 5300 3200 5600 3200 4 0 1
261 
{
262 
T 5200 3200 5  10 1 1 0 7 1 1
263 
pinnumber=rts_pad_out
264 
T 5300 3200 5  10 0 1 0 7 1 1
265 
pinseq=36
266 
}
267 
P 5300 3400 5600 3400 4 0 1
268 
{
269 
T 5200 3400 5  10 1 1 0 7 1 1
270 
pinnumber=ps2_data_pad_oe
271 
T 5300 3400 5  10 0 1 0 7 1 1
272 
pinseq=37
273 
}
274 
P 5300 3600 5600 3600 4 0 1
275 
{
276 
T 5200 3600 5  10 1 1 0 7 1 1
277 
pinnumber=ps2_clk_pad_oe
278 
T 5300 3600 5  10 0 1 0 7 1 1
279 
pinseq=38
280 
}
281 
P 5300 3800 5600 3800 4 0 1
282 
{
283 
T 5200 3800 5  10 1 1 0 7 1 1
284 
pinnumber=jtag_tdo
285 
T 5300 3800 5  10 0 1 0 7 1 1
286 
pinseq=39
287 
}
288 
P 5300 4000 5600 4000 4 0 1
289 
{
290 
T 5200 4000 5  10 1 1 0 7 1 1
291 
pinnumber=ext_wr
292 
T 5300 4000 5  10 0 1 0 7 1 1
293 
pinseq=40
294 
}
295 
P 5300 4200 5600 4200 4 0 1
296 
{
297 
T 5200 4200 5  10 1 1 0 7 1 1
298 
pinnumber=ext_ub
299 
T 5300 4200 5  10 0 1 0 7 1 1
300 
pinseq=41
301 
}
302 
P 5300 4400 5600 4400 4 0 1
303 
{
304 
T 5200 4400 5  10 1 1 0 7 1 1
305 
pinnumber=ext_stb
306 
T 5300 4400 5  10 0 1 0 7 1 1
307 
pinseq=42
308 
}
309 
P 5300 4600 5600 4600 4 0 1
310 
{
311 
T 5200 4600 5  10 1 1 0 7 1 1
312 
pinnumber=ext_rd
313 
T 5300 4600 5  10 0 1 0 7 1 1
314 
pinseq=43
315 
}
316 
P 5300 4800 5600 4800 4 0 1
317 
{
318 
T 5200 4800 5  10 1 1 0 7 1 1
319 
pinnumber=ext_lb
320 
T 5300 4800 5  10 0 1 0 7 1 1
321 
pinseq=44
322 
}
323 
P 5300 5000 5600 5000 4 0 1
324 
{
325 
T 5200 5000 5  10 1 1 0 7 1 1
326 
pinnumber=biu_wr_strobe
327 
T 5300 5000 5  10 0 1 0 7 1 1
328 
pinseq=45
329 
}

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