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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Mos6502
T6502
def_tb
 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      T6502_def_tb
    
  

 
 
 

 
 
 
 

 
 
 
 
 

 
              
              Params
              
              
                                   ipxact:library="Mos6502"
                                   ipxact:name="T6502"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
              
                                   ipxact:library="Mos6502"
                                   ipxact:name="T6502"
                                   ipxact:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common
              :*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint
              :*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext_m
        verilogSourcefragment
      
 
 
   
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/T6502_def_tb
        verilogSourcemodule
      
 
   
 
 
 
   
      fs-lint
 
      
        
        ../verilog/common/T6502_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_tb`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47
48
49
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`T6502_def_tb`
61
62
63
64	131	jt_eaton
65
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72	135	jt_eaton
73	131	jt_eaton
74
75
76
77
78	135	jt_eaton
79	131	jt_eaton
80	135	jt_eaton
81			`Params`
82
83
84			`ipxact:library="Mos6502"`
85			`ipxact:name="T6502"`
86			`ipxact:version="def_dut.params"/>`
87
88
89	131	jt_eaton
90
91
92	135	jt_eaton
93			`Bfm`
94
95
96			`ipxact:library="Mos6502"`
97			`ipxact:name="T6502"`
98			`ipxact:version="bfm"/>`
99
100
101	131	jt_eaton
102
103
104
105
106
107
108	135	jt_eaton
109			`icarus`
110
111
112			`ipxact:library="Testbench"`
113			`ipxact:name="toolflow"`
114			`ipxact:version="icarus"/>`
115
116
117	131	jt_eaton
118
119
120
121	135	jt_eaton
122			`common`
123			`:common:`
124			`Verilog`
125
126
127			`fs-common`
128
129
130	131	jt_eaton
131
132	135	jt_eaton
133			`sim`
134			`:Simulation:`
135			`Verilog`
136
137
138			`fs-sim`
139
140
141	131	jt_eaton
142
143	135	jt_eaton
144			`lint`
145			`:Lint:`
146			`Verilog`
147
148
149			`fs-lint`
150
151
152	131	jt_eaton
153
154	135	jt_eaton
155	131	jt_eaton
156
157	135	jt_eaton
158	131	jt_eaton
159
160
161
162
163	135	jt_eaton
164	131	jt_eaton
165
166
167	135	jt_eaton
168			`fs-common`
169	131	jt_eaton
170	135	jt_eaton
171
172			`../verilog/sram.load`
173			`verilogSourcefragment`
174
175	131	jt_eaton
176
177	135	jt_eaton
178
179			`../verilog/tb.ext_m`
180			`verilogSourcefragment`
181
182	131	jt_eaton
183
184	135	jt_eaton
185	131	jt_eaton
186
187
188
189	135	jt_eaton
190			`fs-sim`
191	131	jt_eaton
192
193
194	135	jt_eaton
195
196			`../verilog/common/T6502_def_tb`
197			`verilogSourcemodule`
198
199	131	jt_eaton
200	135	jt_eaton
201	131	jt_eaton
202
203
204	135	jt_eaton
205			`fs-lint`
206	131	jt_eaton
207	135	jt_eaton
208
209			`../verilog/common/T6502_def_tb`
210			`verilogSourcemodule`
211
212	131	jt_eaton
213
214
215	135	jt_eaton
216	131	jt_eaton
217
218
219
220	135	jt_eaton
221	131	jt_eaton
222
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224	135	jt_eaton
225	131	jt_eaton
226
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