URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [verilog/] [sram.load] - Blame information for rev 135

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parameter PREFIX ="../../../../../../../code/";
 
initial
  begin
  if( PROG_ROM_FILE != "NONE") begin $readmemh({PREFIX,PROG_ROM_FILE},  dut.prog_rom.mem);end
  if( PROG_ROM_FILE != "NONE") begin $readmemh({PREFIX,PROG_ROM_FILE},  sh_prog_rom.mem);end
  if(      ROM_FILE != "NONE") begin $readmemh({PREFIX,ROM_FILE},       boot_rom.mem);end
  end
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`parameter PREFIX ="../../../../../../../code/";`
2	131	jt_eaton
3			`initial`
4			`begin`
5			`if( PROG_ROM_FILE != "NONE") begin $readmemh({PREFIX,PROG_ROM_FILE}, dut.prog_rom.mem);end`
6			`if( PROG_ROM_FILE != "NONE") begin $readmemh({PREFIX,PROG_ROM_FILE}, sh_prog_rom.mem);end`
7			`if( ROM_FILE != "NONE") begin $readmemh({PREFIX,ROM_FILE}, boot_rom.mem);end`
8			`end`
9

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [verilog/] [sram.load] - Blame information for rev 135