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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [doc/] [sym/] [adv_dbg_if_wb_cpu0.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  3800 3500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 3650   5 10 1 1 0 0 1 1
4 
device=adv_dbg_if_wb_cpu0
5 
T 400 3850 5 10 1 1 0 0 1 1
6 
refdes=U?
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T 400 4000    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
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T 400 4000    0 10 0 1 0 0 1 1
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library=adv_debug_sys
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T 400 4000    0 10 0 1 0 0 1 1
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component=adv_dbg_if
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T 400 4000    0 10 0 1 0 0 1 1
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version=wb_cpu0
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P 300 200 0 200 10 1 1
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{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=wb_dat_i[31:0]
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T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 10 1 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=cpu0_data_i[31:0]
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 4 0 1
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{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=wb_rst_i
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 4 0 1
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{
38 
T 400 800 5 10 1 1 0 1 1 1
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pinnumber=wb_err_i
40 
T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
42 
}
43 
P 300 1000 0 1000 4 0 1
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{
45 
T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=wb_clk_i
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
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{
52 
T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=wb_ack_i
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T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=update_dr_i
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
67 
pinnumber=tdi_i
68 
T 400 1600 5 10 0 1 0 1 1 1
69 
pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
72 
{
73 
T 400 1800 5 10 1 1 0 1 1 1
74 
pinnumber=tck_i
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T 400 1800 5 10 0 1 0 1 1 1
76 
pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
79 
{
80 
T 400 2000 5 10 1 1 0 1 1 1
81 
pinnumber=shift_dr_i
82 
T 400 2000 5 10 0 1 0 1 1 1
83 
pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
86 
{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=rst_i
89 
T 400 2200 5 10 0 1 0 1 1 1
90 
pinseq=11
91 
}
92 
P 300 2400 0 2400 4 0 1
93 
{
94 
T 400 2400 5 10 1 1 0 1 1 1
95 
pinnumber=debug_select_i
96 
T 400 2400 5 10 0 1 0 1 1 1
97 
pinseq=12
98 
}
99 
P 300 2600 0 2600 4 0 1
100 
{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=cpu0_clk_i
103 
T 400 2600 5 10 0 1 0 1 1 1
104 
pinseq=13
105 
}
106 
P 300 2800 0 2800 4 0 1
107 
{
108 
T 400 2800 5 10 1 1 0 1 1 1
109 
pinnumber=cpu0_bp_i
110 
T 400 2800 5 10 0 1 0 1 1 1
111 
pinseq=14
112 
}
113 
P 300 3000 0 3000 4 0 1
114 
{
115 
T 400 3000 5 10 1 1 0 1 1 1
116 
pinnumber=cpu0_ack_i
117 
T 400 3000 5 10 0 1 0 1 1 1
118 
pinseq=15
119 
}
120 
P 300 3200 0 3200 4 0 1
121 
{
122 
T 400 3200 5 10 1 1 0 1 1 1
123 
pinnumber=capture_dr_i
124 
T 400 3200 5 10 0 1 0 1 1 1
125 
pinseq=16
126 
}
127 
P 4100 200 4400 200 10 1 1
128 
{
129 
T 4000 200 5  10 1 1 0 7 1 1
130 
pinnumber=wb_sel_o[3:0]
131 
T 4000 200 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 4100 400 4400 400 10 1 1
135 
{
136 
T 4000 400 5  10 1 1 0 7 1 1
137 
pinnumber=wb_dat_o[31:0]
138 
T 4000 400 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}
141 
P 4100 600 4400 600 10 1 1
142 
{
143 
T 4000 600 5  10 1 1 0 7 1 1
144 
pinnumber=wb_cti_o[2:0]
145 
T 4000 600 5  10 0 1 0 7 1 1
146 
pinseq=19
147 
}
148 
P 4100 800 4400 800 10 1 1
149 
{
150 
T 4000 800 5  10 1 1 0 7 1 1
151 
pinnumber=wb_bte_o[1:0]
152 
T 4000 800 5  10 0 1 0 7 1 1
153 
pinseq=20
154 
}
155 
P 4100 1000 4400 1000 10 1 1
156 
{
157 
T 4000 1000 5  10 1 1 0 7 1 1
158 
pinnumber=wb_adr_o[31:0]
159 
T 4000 1000 5  10 0 1 0 7 1 1
160 
pinseq=21
161 
}
162 
P 4100 1200 4400 1200 10 1 1
163 
{
164 
T 4000 1200 5  10 1 1 0 7 1 1
165 
pinnumber=cpu0_data_o[31:0]
166 
T 4000 1200 5  10 0 1 0 7 1 1
167 
pinseq=22
168 
}
169 
P 4100 1400 4400 1400 10 1 1
170 
{
171 
T 4000 1400 5  10 1 1 0 7 1 1
172 
pinnumber=cpu0_addr_o[31:0]
173 
T 4000 1400 5  10 0 1 0 7 1 1
174 
pinseq=23
175 
}
176 
P 4100 1600 4400 1600 4 0 1
177 
{
178 
T 4000 1600 5  10 1 1 0 7 1 1
179 
pinnumber=wb_we_o
180 
T 4100 1600 5  10 0 1 0 7 1 1
181 
pinseq=24
182 
}
183 
P 4100 1800 4400 1800 4 0 1
184 
{
185 
T 4000 1800 5  10 1 1 0 7 1 1
186 
pinnumber=wb_stb_o
187 
T 4100 1800 5  10 0 1 0 7 1 1
188 
pinseq=25
189 
}
190 
P 4100 2000 4400 2000 4 0 1
191 
{
192 
T 4000 2000 5  10 1 1 0 7 1 1
193 
pinnumber=wb_cyc_o
194 
T 4100 2000 5  10 0 1 0 7 1 1
195 
pinseq=26
196 
}
197 
P 4100 2200 4400 2200 4 0 1
198 
{
199 
T 4000 2200 5  10 1 1 0 7 1 1
200 
pinnumber=wb_cab_o
201 
T 4100 2200 5  10 0 1 0 7 1 1
202 
pinseq=27
203 
}
204 
P 4100 2400 4400 2400 4 0 1
205 
{
206 
T 4000 2400 5  10 1 1 0 7 1 1
207 
pinnumber=tdo_o
208 
T 4100 2400 5  10 0 1 0 7 1 1
209 
pinseq=28
210 
}
211 
P 4100 2600 4400 2600 4 0 1
212 
{
213 
T 4000 2600 5  10 1 1 0 7 1 1
214 
pinnumber=cpu0_we_o
215 
T 4100 2600 5  10 0 1 0 7 1 1
216 
pinseq=29
217 
}
218 
P 4100 2800 4400 2800 4 0 1
219 
{
220 
T 4000 2800 5  10 1 1 0 7 1 1
221 
pinnumber=cpu0_stb_o
222 
T 4100 2800 5  10 0 1 0 7 1 1
223 
pinseq=30
224 
}
225 
P 4100 3000 4400 3000 4 0 1
226 
{
227 
T 4000 3000 5  10 1 1 0 7 1 1
228 
pinnumber=cpu0_stall_o
229 
T 4100 3000 5  10 0 1 0 7 1 1
230 
pinseq=31
231 
}
232 
P 4100 3200 4400 3200 4 0 1
233 
{
234 
T 4000 3200 5  10 1 1 0 7 1 1
235 
pinnumber=cpu0_rst_o
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T 4100 3200 5  10 0 1 0 7 1 1
237 
pinseq=32
238 
}

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