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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
cpu0_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      adv_dbg_if_cpu0_tb
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
       
 
              
              Params
              
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="cpu0_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="adv_debug_sys"
                                   ipxact:name="adv_dbg_if"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
 
 
      
        
        ../verilog/tb.cpu0
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/adv_dbg_if_cpu0_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/adv_dbg_if_cpu0_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`cpu0_tb`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`adv_dbg_if_cpu0_tb`
34
35
36
37	131	jt_eaton
38
39
40	135	jt_eaton
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50			`JTAG_MODEL_DIVCNT 4'h4`
51			`JTAG_MODEL_SIZE 4`
52
53	131	jt_eaton
54	135	jt_eaton
55	131	jt_eaton
56	135	jt_eaton
57			`Params`
58
59
60			`ipxact:library="adv_debug_sys"`
61			`ipxact:name="adv_dbg_if"`
62			`ipxact:version="cpu0_dut.params"/>`
63
64
65	131	jt_eaton
66
67	135	jt_eaton
68			`Bfm`
69
70			`ipxact:library="adv_debug_sys"`
71			`ipxact:name="adv_dbg_if"`
72			`ipxact:version="bfm.design"/>`
73
74	131	jt_eaton
75
76	135	jt_eaton
77			`icarus`
78
79
80			`ipxact:library="Testbench"`
81			`ipxact:name="toolflow"`
82			`ipxact:version="icarus"/>`
83
84
85	131	jt_eaton
86
87
88
89	135	jt_eaton
90			`common:common:`
91			`Verilog`
92
93
94			`fs-common`
95
96
97	131	jt_eaton
98
99	135	jt_eaton
100			`sim:Simulation:`
101			`Verilog`
102
103
104			`fs-sim`
105
106
107	131	jt_eaton
108	135	jt_eaton
109			`lint:Lint:`
110			`Verilog`
111
112
113			`fs-lint`
114
115
116	131	jt_eaton
117	135	jt_eaton
118	131	jt_eaton
119
120
121
122	135	jt_eaton
123	131	jt_eaton
124
125
126
127
128	135	jt_eaton
129	131	jt_eaton
130
131
132
133	135	jt_eaton
134			`fs-common`
135	131	jt_eaton
136
137
138
139	135	jt_eaton
140
141			`../verilog/tb.cpu0`
142			`verilogSource`
143			`fragment`
144
145	131	jt_eaton
146
147
148
149
150
151
152
153	135	jt_eaton
154	131	jt_eaton
155
156
157
158
159	135	jt_eaton
160			`fs-sim`
161	131	jt_eaton
162
163	135	jt_eaton
164
165			`../verilog/tb.ext`
166			`verilogSource`
167			`fragment`
168
169	131	jt_eaton
170
171
172
173	135	jt_eaton
174
175			`../verilog/common/adv_dbg_if_cpu0_tb`
176			`verilogSourcemodule`
177
178	131	jt_eaton
179
180
181
182	135	jt_eaton
183	131	jt_eaton
184
185	135	jt_eaton
186			`fs-lint`
187
188
189			`../verilog/common/adv_dbg_if_cpu0_tb`
190			`verilogSourcemodule`
191
192	131	jt_eaton
193
194	135	jt_eaton
195	131	jt_eaton
196
197
198
199
200	135	jt_eaton
201	131	jt_eaton
202
203
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205
206	135	jt_eaton