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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_bfm.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb_bfm.design
 
 
 
 

 
 
 
  
      clk
      
      
    
 
  
      reset
      
      
    
 
 
 
 
 

 
 
 
 
 
    
      wb
      
          
          
          adr
          
          wb_adr_o
          310
          
          
 
 
          
          wdata
          
          wb_dat_o
          310
          
          
 
 
          
          rdata
          
          wb_dat_i
          310
          
          
 
 
          
          sel
          
          wb_sel_o
          wb_byte_lanes-10
          
          
 
          
          ack
          
          wb_ack_i
          
          
 
          
          cyc
          
          wb_cyc_o
          
          
 
          
          stb
          
          wb_stb_o
          
          
 
          
          we
          
          wb_we_o
          
          
 
          
      
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 

wb_ram 

 wb_addr_width
 32
 14
 65536
 "NONE"
 "NONE"
 "NONE"
 "NONE"


 
 
 
 
 
 
 

 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb_bfm.design`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48
49	135	jt_eaton
50			`clk`
51
52
53
54	131	jt_eaton
55	135	jt_eaton
56			`reset`
57
58
59
60	131	jt_eaton
61
62
63
64
65	135	jt_eaton
66	131	jt_eaton
67
68	135	jt_eaton
69	131	jt_eaton
70
71	135	jt_eaton
72			`wb`
73
74
75
76			`adr`
77
78			`wb_adr_o`
79			`310`
80
81
82	131	jt_eaton
83
84	135	jt_eaton
85			`wdata`
86
87			`wb_dat_o`
88			`310`
89
90
91	131	jt_eaton
92
93	135	jt_eaton
94			`rdata`
95
96			`wb_dat_i`
97			`310`
98
99
100	131	jt_eaton
101
102	135	jt_eaton
103			`sel`
104
105			`wb_sel_o`
106			`wb_byte_lanes-10`
107
108
109	131	jt_eaton
110	135	jt_eaton
111			`ack`
112
113			`wb_ack_i`
114
115
116	131	jt_eaton
117	135	jt_eaton
118			`cyc`
119
120			`wb_cyc_o`
121
122
123	131	jt_eaton
124	135	jt_eaton
125			`stb`
126
127			`wb_stb_o`
128
129
130	131	jt_eaton
131	135	jt_eaton
132			`we`
133
134			`wb_we_o`
135
136
137	131	jt_eaton
138	135	jt_eaton
139
140	131	jt_eaton
141
142	135	jt_eaton
143	131	jt_eaton
144
145
146
147
148
149
150
151
152
153	135	jt_eaton
154	131	jt_eaton
155
156
157
158
159	135	jt_eaton
160	131	jt_eaton
161
162	135	jt_eaton
163			`wb_ram`
164
165			`wb_addr_width`
166			`32`
167			`14`
168			`65536`
169			`"NONE"`
170			`"NONE"`
171			`"NONE"`
172			`"NONE"`
173
174
175	131	jt_eaton
176
177
178
179
180
181
182	135	jt_eaton
183	131	jt_eaton
184
185	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_wb_bfm.design.xml] - Blame information for rev 135