URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_fpga.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
fpga.design
 
 

 
 
 
 

core


RAM_WORDS
RAM_ADD
ROM_WORDS
ROM_ADD
PROG_ROM_WORDS
PROG_ROM_ADD
VEC_TABLE
UART_PRESCALE
UART_PRE_SIZE
UART_DIV
JTAG_USER1_WIDTH
JTAG_USER1_RESET


 
 
 

 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`fpga.design`
40	131	jt_eaton
41
42	135	jt_eaton
43	131	jt_eaton
44
45
46
47	135	jt_eaton
48			`core`
49
50
51			`RAM_WORDS`
52			`RAM_ADD`
53			`ROM_WORDS`
54			`ROM_ADD`
55			`PROG_ROM_WORDS`
56			`PROG_ROM_ADD`
57			`VEC_TABLE`
58			`UART_PRESCALE`
59			`UART_PRE_SIZE`
60			`UART_DIV`
61			`JTAG_USER1_WIDTH`
62			`JTAG_USER1_RESET`
63
64
65	131	jt_eaton
66
67
68	135	jt_eaton
69	131	jt_eaton
70
71
72
73	135	jt_eaton
74	131	jt_eaton
75
76
77
78
79

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_fpga.design.xml] - Blame information for rev 135