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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_tb
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      Nexys2_T6502_default_tb
    
  

 
 
 

 
 
 
 
 


    JTAG_MODEL_DIVCNT 4'h4     
    JTAG_MODEL_SIZE   4        
    UART_MODEL_CLKCNT 5'b11001 
    UART_MODEL_SIZE   5        
    PS2_MODEL_CLKCNT  10'h177  
    PS2_MODEL_SIZE    10       
 

       
 
 
 
              
              Params
              
              
                                   ipxact:library="fpgas"
                                   ipxact:name="Nexys2_T6502"
                                   ipxact:version="default_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   ipxact:library="fpgas"
                                   ipxact:name="Nexys2_T6502"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/Nexys2_T6502_default_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default_tb`
40	131	jt_eaton
41
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47	135	jt_eaton
48			`gen_verilog`
49			`104.0`
50			`none`
51			`:common:`
52			`tools/verilog/gen_verilog`
53
54
55			`destination`
56			`Nexys2_T6502_default_tb`
57
58
59
60	131	jt_eaton
61
62
63	135	jt_eaton
64	131	jt_eaton
65
66
67
68
69	135	jt_eaton
70
71			`JTAG_MODEL_DIVCNT 4'h4`
72			`JTAG_MODEL_SIZE 4`
73			`UART_MODEL_CLKCNT 5'b11001`
74			`UART_MODEL_SIZE 5`
75			`PS2_MODEL_CLKCNT 10'h177`
76			`PS2_MODEL_SIZE 10`
77	131	jt_eaton
78	135	jt_eaton
79
80	131	jt_eaton
81
82
83	135	jt_eaton
84			`Params`
85
86
87			`ipxact:library="fpgas"`
88			`ipxact:name="Nexys2_T6502"`
89			`ipxact:version="default_dut.params"/>`
90
91
92	131	jt_eaton
93
94
95	135	jt_eaton
96			`Bfm`
97
98			`ipxact:library="fpgas"`
99			`ipxact:name="Nexys2_T6502"`
100			`ipxact:version="bfm.design"/>`
101
102	131	jt_eaton
103
104
105	135	jt_eaton
106			`icarus`
107
108
109			`ipxact:library="Testbench"`
110			`ipxact:name="toolflow"`
111			`ipxact:version="icarus"/>`
112
113
114	131	jt_eaton
115
116
117
118	135	jt_eaton
119			`common:common:`
120			`Verilog`
121
122
123			`fs-common`
124
125
126	131	jt_eaton
127
128	135	jt_eaton
129			`sim:Simulation:`
130			`Verilog`
131
132
133			`fs-sim`
134
135
136	131	jt_eaton
137	135	jt_eaton
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145	131	jt_eaton
146	135	jt_eaton
147	131	jt_eaton
148
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154	135	jt_eaton
155	131	jt_eaton
156
157
158	135	jt_eaton
159			`fs-common`
160	131	jt_eaton
161	135	jt_eaton
162
163			`../verilog/sram.load`
164			`verilogSourcefragment`
165
166	131	jt_eaton
167
168	135	jt_eaton
169
170			`../verilog/tb.ext`
171			`verilogSourcefragment`
172
173	131	jt_eaton
174
175
176	135	jt_eaton
177	131	jt_eaton
178
179
180
181	135	jt_eaton
182			`fs-sim`
183	131	jt_eaton
184	135	jt_eaton
185
186			`../verilog/common/Nexys2_T6502_default_tb`
187			`verilogSourcemodule`
188
189	131	jt_eaton
190	135	jt_eaton
191	131	jt_eaton
192
193
194
195
196
197
198	135	jt_eaton
199	131	jt_eaton
200
201
202	135	jt_eaton
203	131	jt_eaton
204
205
206
207
208

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 135