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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sch/] [io_ext_mem_interface_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1700 300 1 0 0 in_port_vector.sym
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{
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T 1700 300 5 10 1 1 0 6 1 1
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refdes=wdata[7:0]
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}
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C 1700 700 1 0 0 in_port_vector.sym
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{
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T 1700 700 5 10 1 1 0 6 1 1
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refdes=mem_wdata[15:0]
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}
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C 1700 1100 1 0 0 in_port_vector.sym
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{
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T 1700 1100 5 10 1 1 0 6 1 1
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refdes=mem_addr[13:0]
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}
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C 1700 1500 1 0 0 in_port_vector.sym
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{
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T 1700 1500 5 10 1 1 0 6 1 1
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refdes=ext_rdata[15:0]
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}
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C 1700 1900 1 0 0 in_port_vector.sym
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{
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T 1700 1900 5 10 1 1 0 6 1 1
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refdes=addr[3:0]
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}
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C 1700 2300 1 0 0 in_port.sym
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{
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T 1700 2300 5 10 1 1 0 6 1 1
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refdes=wr
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}
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C 1700 2700 1 0 0 in_port.sym
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{
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T 1700 2700 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1700 3100 1 0 0 in_port.sym
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{
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T 1700 3100 5 10 1 1 0 6 1 1
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refdes=rd
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}
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C 1700 3500 1 0 0 in_port.sym
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{
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T 1700 3500 5 10 1 1 0 6 1 1
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refdes=mem_wr
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}
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C 1700 3900 1 0 0 in_port.sym
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{
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T 1700 3900 5 10 1 1 0 6 1 1
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refdes=mem_rd
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}
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C 1700 4300 1 0 0 in_port.sym
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{
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T 1700 4300 5 10 1 1 0 6 1 1
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refdes=mem_cs
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}
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C 1700 4700 1 0 0 in_port.sym
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{
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T 1700 4700 5 10 1 1 0 6 1 1
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refdes=ext_wait
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}
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C 1700 5100 1 0 0 in_port.sym
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{
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T 1700 5100 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 1700 5500 1 0 0 in_port.sym
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{
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T 1700 5500 5 10 1 1 0 6 1 1
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refdes=cs
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}
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C 1700 5900 1 0 0 in_port.sym
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{
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T 1700 5900 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 4500 300  1 0  0 out_port_vector.sym
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{
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T 5500 300 5  10 1 1 0 0 1 1
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refdes=wait_st[7:0]
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}
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C 4500 700  1 0  0 out_port_vector.sym
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{
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T 5500 700 5  10 1 1 0 0 1 1
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refdes=rdata[7:0]
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}
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C 4500 1100  1 0  0 out_port_vector.sym
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{
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T 5500 1100 5  10 1 1 0 0 1 1
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refdes=mem_rdata[15:0]
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}
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C 4500 1500  1 0  0 out_port_vector.sym
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{
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T 5500 1500 5  10 1 1 0 0 1 1
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refdes=ext_wdata[15:0]
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}
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C 4500 1900  1 0  0 out_port_vector.sym
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{
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T 5500 1900 5  10 1 1 0 0 1 1
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refdes=ext_cs[1:0]
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}
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C 4500 2300  1 0  0 out_port_vector.sym
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{
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T 5500 2300 5  10 1 1 0 0 1 1
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refdes=ext_addr[23:0]
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}
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C 4500 2700  1 0  0 out_port_vector.sym
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{
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T 5500 2700 5  10 1 1 0 0 1 1
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refdes=ext_add[23:1]
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}
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C 4500 3100  1 0  0 out_port_vector.sym
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{
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T 5500 3100 5  10 1 1 0 0 1 1
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refdes=bank[7:0]
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}
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C 4500 3500  1 0 0 out_port.sym
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{
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T 5500 3500 5  10 1 1 0 0 1 1
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refdes=mem_wait
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}
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C 4500 3900  1 0 0 out_port.sym
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{
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T 5500 3900 5  10 1 1 0 0 1 1
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refdes=ext_wr
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}
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C 4500 4300  1 0 0 out_port.sym
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{
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T 5500 4300 5  10 1 1 0 0 1 1
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refdes=ext_ub
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}
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C 4500 4700  1 0 0 out_port.sym
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{
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T 5500 4700 5  10 1 1 0 0 1 1
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refdes=ext_stb
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}
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C 4500 5100  1 0 0 out_port.sym
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{
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T 5500 5100 5  10 1 1 0 0 1 1
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refdes=ext_rd
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}
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C 4500 5500  1 0 0 out_port.sym
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{
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T 5500 5500 5  10 1 1 0 0 1 1
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refdes=ext_lb
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}

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