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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [doc/] [sch/] [io_module_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 1900 300 1 0 0 in_port_vector.sym
3 
{
4 
T 1900 300 5 10 1 1 0 6 1 1
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refdes=vic_irq_in[7:0]
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}
7 
C 1900 700 1 0 0 in_port_vector.sym
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{
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T 1900 700 5 10 1 1 0 6 1 1
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refdes=reg_mb_wdata[7:0]
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}
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C 1900 1100 1 0 0 in_port_vector.sym
13 
{
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T 1900 1100 5 10 1 1 0 6 1 1
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refdes=reg_mb_addr[7:0]
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}
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C 1900 1500 1 0 0 in_port_vector.sym
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{
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T 1900 1500 5 10 1 1 0 6 1 1
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refdes=pic_irq_in[7:0]
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}
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C 1900 1900 1 0 0 in_port_vector.sym
23 
{
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T 1900 1900 5 10 1 1 0 6 1 1
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refdes=mem_wdata[15:0]
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}
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C 1900 2300 1 0 0 in_port_vector.sym
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{
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T 1900 2300 5 10 1 1 0 6 1 1
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refdes=mem_addr[13:0]
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}
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C 1900 2700 1 0 0 in_port_vector.sym
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{
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T 1900 2700 5 10 1 1 0 6 1 1
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refdes=gpio_1_in[7:0]
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}
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C 1900 3100 1 0 0 in_port_vector.sym
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{
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T 1900 3100 5 10 1 1 0 6 1 1
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refdes=gpio_0_in[7:0]
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}
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C 1900 3500 1 0 0 in_port_vector.sym
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{
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T 1900 3500 5 10 1 1 0 6 1 1
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refdes=ext_rdata[15:0]
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}
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C 1900 3900 1 0 0 in_port.sym
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{
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T 1900 3900 5 10 1 1 0 6 1 1
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refdes=uart_rxd_pad_in
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}
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C 1900 4300 1 0 0 in_port.sym
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{
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T 1900 4300 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1900 4700 1 0 0 in_port.sym
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{
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T 1900 4700 5 10 1 1 0 6 1 1
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refdes=reg_mb_wr
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}
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C 1900 5100 1 0 0 in_port.sym
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{
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T 1900 5100 5 10 1 1 0 6 1 1
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refdes=reg_mb_rd
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}
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C 1900 5500 1 0 0 in_port.sym
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{
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T 1900 5500 5 10 1 1 0 6 1 1
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refdes=reg_mb_cs
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}
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C 1900 5900 1 0 0 in_port.sym
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{
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T 1900 5900 5 10 1 1 0 6 1 1
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refdes=ps2_data_pad_in
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}
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C 1900 6300 1 0 0 in_port.sym
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{
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T 1900 6300 5 10 1 1 0 6 1 1
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refdes=ps2_clk_pad_in
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}
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C 1900 6700 1 0 0 in_port.sym
83 
{
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T 1900 6700 5 10 1 1 0 6 1 1
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refdes=mem_wr
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}
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C 1900 7100 1 0 0 in_port.sym
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{
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T 1900 7100 5 10 1 1 0 6 1 1
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refdes=mem_rd
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}
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C 1900 7500 1 0 0 in_port.sym
93 
{
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T 1900 7500 5 10 1 1 0 6 1 1
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refdes=mem_cs
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}
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C 1900 7900 1 0 0 in_port.sym
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{
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T 1900 7900 5 10 1 1 0 6 1 1
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refdes=ext_wait
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}
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C 1900 8300 1 0 0 in_port.sym
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{
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T 1900 8300 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 1900 8700 1 0 0 in_port.sym
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{
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T 1900 8700 5 10 1 1 0 6 1 1
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refdes=cts_pad_in
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}
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C 1900 9100 1 0 0 in_port.sym
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{
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T 1900 9100 5 10 1 1 0 6 1 1
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refdes=clk
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}
117 
C 5400 300  1 0  0 out_port_vector.sym
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{
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T 6400 300 5  10 1 1 0 0 1 1
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refdes=y_pos[9:0]
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}
122 
C 5400 700  1 0  0 out_port_vector.sym
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{
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T 6400 700 5  10 1 1 0 0 1 1
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refdes=x_pos[9:0]
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}
127 
C 5400 1100  1 0  0 out_port_vector.sym
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{
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T 6400 1100 5  10 1 1 0 0 1 1
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refdes=vga_red_pad_out[2:0]
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}
132 
C 5400 1500  1 0  0 out_port_vector.sym
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{
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T 6400 1500 5  10 1 1 0 0 1 1
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refdes=vga_green_pad_out[2:0]
136 
}
137 
C 5400 1900  1 0  0 out_port_vector.sym
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{
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T 6400 1900 5  10 1 1 0 0 1 1
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refdes=vga_blue_pad_out[1:0]
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}
142 
C 5400 2300  1 0  0 out_port_vector.sym
143 
{
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T 6400 2300 5  10 1 1 0 0 1 1
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refdes=vector[7:0]
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}
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C 5400 2700  1 0  0 out_port_vector.sym
148 
{
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T 6400 2700 5  10 1 1 0 0 1 1
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refdes=timer_irq[1:0]
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}
152 
C 5400 3100  1 0  0 out_port_vector.sym
153 
{
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T 6400 3100 5  10 1 1 0 0 1 1
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refdes=reg_mb_rdata[15:0]
156 
}
157 
C 5400 3500  1 0  0 out_port_vector.sym
158 
{
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T 6400 3500 5  10 1 1 0 0 1 1
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refdes=mem_rdata[15:0]
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}
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C 5400 3900  1 0  0 out_port_vector.sym
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{
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T 6400 3900 5  10 1 1 0 0 1 1
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refdes=gpio_1_out[7:0]
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}
167 
C 5400 4300  1 0  0 out_port_vector.sym
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{
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T 6400 4300 5  10 1 1 0 0 1 1
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refdes=gpio_1_oe[7:0]
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}
172 
C 5400 4700  1 0  0 out_port_vector.sym
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{
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T 6400 4700 5  10 1 1 0 0 1 1
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refdes=gpio_0_out[7:0]
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}
177 
C 5400 5100  1 0  0 out_port_vector.sym
178 
{
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T 6400 5100 5  10 1 1 0 0 1 1
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refdes=gpio_0_oe[7:0]
181 
}
182 
C 5400 5500  1 0  0 out_port_vector.sym
183 
{
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T 6400 5500 5  10 1 1 0 0 1 1
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refdes=ext_wdata[15:0]
186 
}
187 
C 5400 5900  1 0  0 out_port_vector.sym
188 
{
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T 6400 5900 5  10 1 1 0 0 1 1
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refdes=ext_cs[1:0]
191 
}
192 
C 5400 6300  1 0  0 out_port_vector.sym
193 
{
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T 6400 6300 5  10 1 1 0 0 1 1
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refdes=ext_addr[23:1]
196 
}
197 
C 5400 6700  1 0 0 out_port.sym
198 
{
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T 6400 6700 5  10 1 1 0 0 1 1
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refdes=vga_vsync_n_pad_out
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}
202 
C 5400 7100  1 0 0 out_port.sym
203 
{
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T 6400 7100 5  10 1 1 0 0 1 1
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refdes=vga_hsync_n_pad_out
206 
}
207 
C 5400 7500  1 0 0 out_port.sym
208 
{
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T 6400 7500 5  10 1 1 0 0 1 1
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refdes=uart_txd_pad_out
211 
}
212 
C 5400 7900  1 0 0 out_port.sym
213 
{
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T 6400 7900 5  10 1 1 0 0 1 1
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refdes=tx_irq
216 
}
217 
C 5400 8300  1 0 0 out_port.sym
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{
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T 6400 8300 5  10 1 1 0 0 1 1
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refdes=rx_irq
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}
222 
C 5400 8700  1 0 0 out_port.sym
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{
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T 6400 8700 5  10 1 1 0 0 1 1
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refdes=rts_pad_out
226 
}
227 
C 5400 9100  1 0 0 out_port.sym
228 
{
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T 6400 9100 5  10 1 1 0 0 1 1
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refdes=reg_mb_wait
231 
}
232 
C 5400 9500  1 0 0 out_port.sym
233 
{
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T 6400 9500 5  10 1 1 0 0 1 1
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refdes=ps2_data_pad_oe
236 
}
237 
C 5400 9900  1 0 0 out_port.sym
238 
{
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T 6400 9900 5  10 1 1 0 0 1 1
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refdes=ps2_data_avail
241 
}
242 
C 5400 10300  1 0 0 out_port.sym
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{
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T 6400 10300 5  10 1 1 0 0 1 1
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refdes=ps2_clk_pad_oe
246 
}
247 
C 5400 10700  1 0 0 out_port.sym
248 
{
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T 6400 10700 5  10 1 1 0 0 1 1
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refdes=pic_nmi
251 
}
252 
C 5400 11100  1 0 0 out_port.sym
253 
{
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T 6400 11100 5  10 1 1 0 0 1 1
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refdes=pic_irq
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}
257 
C 5400 11500  1 0 0 out_port.sym
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{
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T 6400 11500 5  10 1 1 0 0 1 1
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refdes=new_packet
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}
262 
C 5400 11900  1 0 0 out_port.sym
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{
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T 6400 11900 5  10 1 1 0 0 1 1
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refdes=ms_right
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}
267 
C 5400 12300  1 0 0 out_port.sym
268 
{
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T 6400 12300 5  10 1 1 0 0 1 1
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refdes=ms_mid
271 
}
272 
C 5400 12700  1 0 0 out_port.sym
273 
{
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T 6400 12700 5  10 1 1 0 0 1 1
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refdes=ms_left
276 
}
277 
C 5400 13100  1 0 0 out_port.sym
278 
{
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T 6400 13100 5  10 1 1 0 0 1 1
280 
refdes=mem_wait
281 
}
282 
C 5400 13500  1 0 0 out_port.sym
283 
{
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T 6400 13500 5  10 1 1 0 0 1 1
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refdes=int_out
286 
}
287 
C 5400 13900  1 0 0 out_port.sym
288 
{
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T 6400 13900 5  10 1 1 0 0 1 1
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refdes=ext_wr
291 
}
292 
C 5400 14300  1 0 0 out_port.sym
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{
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T 6400 14300 5  10 1 1 0 0 1 1
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refdes=ext_ub
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}
297 
C 5400 14700  1 0 0 out_port.sym
298 
{
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T 6400 14700 5  10 1 1 0 0 1 1
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refdes=ext_stb
301 
}
302 
C 5400 15100  1 0 0 out_port.sym
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{
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T 6400 15100 5  10 1 1 0 0 1 1
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refdes=ext_rd
306 
}
307 
C 5400 15500  1 0 0 out_port.sym
308 
{
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T 6400 15500 5  10 1 1 0 0 1 1
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refdes=ext_lb
311 
}

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