URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_ext_mem_interface
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
 
     
        
         rdata
         
         rdata
           70
         
       
 
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
 
        
         cs
         
         cs
         
       
 
 
      
 
 
        
      
 
 
 
   little
   8
     
 
 
  
 
 
 
 
 
 
 
 
 
mem
   
   
      
   
   
 
        
         addr
         
         mem_addr
           130
         
       
 
        
         cs
         
         mem_cs
         
       
 
 
        
         rdata
         
         mem_rdata
           150
         
       
 
 
 
        
         wdata
         
         mem_wdata
           150
         
       
 
 
        
         rd
         
         mem_rd
         
       
 
        
         wr
         
         mem_wr
         
       
 
 
        
         wait
         
         mem_wait
         
       
 
 
   
 
 
 
        
      
 
 
 
     
 
 
 
  
 
 
 
 
 
 
 
 
ext
   
   
      
   
     
 
        
         addr
         
         ext_add
                    reg
           231
         
       
 
 
        
         wdata
         
         ext_wdata
           reg
           150
         
       
 
 
        
         rdata
         
         ext_rdata
           wire
           150
         
       
 
 
        
         rd
         
         ext_rd
           reg
         
       
 
 
        
         wr
         
         ext_wr
           reg
         
       
 
 
        
         wait
         
         ext_wait
           wire
         
       
 
 
        
         cs
         
         ext_cs
           reg
           10
         
       
 
 
 
      
 
 
        
      
 
   
 
  
 
 
 
 
 

 
 

 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_ext_mem_interface_def
    
  

 
 
 
 

 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
      
        
        ../verilog/common/io_ext_mem_interface_def
        verilogSourcemodule
      
 
 
      
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_ext_mem_interface_def
        verilogSourcemodule
      
 
 
   
        mb
        ../verilog/io_ext_mem_interface_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
  
 
 
 
 
 
  
 
        
                        
                                Hierarchical
                                
                        
                
 
 
 
 
       
 
              
              Hierarchical
               Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
enable
wire
in

 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
 
 
 
 
 
wait_st
wire
out
70

 
 
 
 
 
 
bank
wire
out
70

 
 
 
 
 
 
 
 
mem_cs
wire
in

 
 
mem_rd
wire
in

 
mem_wr
wire
in

 
 
mem_addr
wire
in
130

 
 
mem_wdata
wire
in
150

 
 
mem_rdata
wire
out
150

 
 
 
 
 
 
ext_cs
wire
out

 
 
ext_rd
wire
out

 
ext_wr
wire
out

 
 
ext_addr
wire
out
230

 
 
ext_wdata
wire
out
150

 
 
ext_rdata
wire
in
150

 
 
 
 
 
 
 
 
ext_ub
reg
out

 
ext_stb
reg
out

 
 
 
ext_lb
reg
out

 
 
 

 

 
 
 
 
 
 

 

 mb
 8
 
   mb
   0x0
   
    ext_mem
    0x10
    8
     
     bank
     0x2
     8
     read-write
     
     
     wait_st
     0x0
     8
     read-write
     
    
   

 
 
 

 mem
 8
 
   mem
   0x0
   
    mem
    0x4000
    16
    
   

 
 
 
 
 
 
 
 

 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ext_mem_interface/] [rtl/] [xml/] [io_ext_mem_interface_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_ext_mem_interface`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81	135	jt_eaton	`mb`
82
83
84
85
86
87
88
89			`rdata`
90
91			`rdata`
92			`70`
93
94
95
96
97
98			`addr`
99
100			`addr`
101			`30`
102
103
104
105
106			`wdata`
107
108			`wdata`
109			`70`
110
111
112
113
114
115			`rd`
116
117			`rd`
118
119
120
121
122			`wr`
123
124			`wr`
125
126
127
128
129
130			`cs`
131
132			`cs`
133
134
135
136
137
138
139
140
141
142
143
144
145			`little`
146			`8`
147
148	131	jt_eaton
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156
157
158
159
160	135	jt_eaton	`mem`
161
162
163
164
165
166	131	jt_eaton
167	135	jt_eaton
168			`addr`
169
170			`mem_addr`
171			`130`
172
173
174	131	jt_eaton
175	135	jt_eaton
176			`cs`
177
178			`mem_cs`
179
180
181	131	jt_eaton
182
183	135	jt_eaton
184			`rdata`
185
186			`mem_rdata`
187			`150`
188
189
190	131	jt_eaton
191
192
193	135	jt_eaton
194			`wdata`
195
196			`mem_wdata`
197			`150`
198
199
200	131	jt_eaton
201
202	135	jt_eaton
203			`rd`
204
205			`mem_rd`
206
207
208	131	jt_eaton
209	135	jt_eaton
210			`wr`
211
212			`mem_wr`
213
214
215	131	jt_eaton
216
217	135	jt_eaton
218			`wait`
219
220			`mem_wait`
221
222
223	131	jt_eaton
224
225	135	jt_eaton
226	131	jt_eaton
227	135	jt_eaton
228	131	jt_eaton
229	135	jt_eaton
230
231	131	jt_eaton
232
233
234	135	jt_eaton
235	131	jt_eaton
236
237
238	135	jt_eaton
239	131	jt_eaton
240
241
242
243
244
245
246
247	135	jt_eaton	`ext`
248
249
250
251
252
253	131	jt_eaton
254	135	jt_eaton
255			`addr`
256
257			`ext_add`
258			`reg`
259			`231`
260
261
262	131	jt_eaton
263
264	135	jt_eaton
265			`wdata`
266
267			`ext_wdata`
268			`reg`
269			`150`
270
271
272	131	jt_eaton
273
274	135	jt_eaton
275			`rdata`
276
277			`ext_rdata`
278			`wire`
279			`150`
280
281
282	131	jt_eaton
283
284	135	jt_eaton
285			`rd`
286
287			`ext_rd`
288			`reg`
289
290
291	131	jt_eaton
292
293	135	jt_eaton
294			`wr`
295
296			`ext_wr`
297			`reg`
298
299
300	131	jt_eaton
301
302	135	jt_eaton
303			`wait`
304
305			`ext_wait`
306			`wire`
307
308
309	131	jt_eaton
310
311	135	jt_eaton
312			`cs`
313
314			`ext_cs`
315			`reg`
316			`10`
317
318
319	131	jt_eaton
320
321
322	135	jt_eaton
323	131	jt_eaton
324
325	135	jt_eaton
326
327	131	jt_eaton
328	135	jt_eaton
329	131	jt_eaton
330	135	jt_eaton
331	131	jt_eaton
332
333
334
335
336	135	jt_eaton
337	131	jt_eaton
338
339	135	jt_eaton
340	131	jt_eaton
341
342
343
344
345
346	135	jt_eaton
347			`gen_registers`
348			`102.1`
349			`:common:`
350			`none`
351			`tools/regtool/gen_registers`
352
353
354			`bus_intf`
355			`mb`
356
357
358			`dest_dir`
359			`../verilog`
360
361
362
363	131	jt_eaton
364	135	jt_eaton
365			`gen_verilog`
366			`104.0`
367			`none`
368			`:common:`
369			`tools/verilog/gen_verilog`
370
371
372			`destination`
373			`io_ext_mem_interface_def`
374
375
376
377	131	jt_eaton
378
379
380
381	135	jt_eaton
382	131	jt_eaton
383
384	135	jt_eaton
385	131	jt_eaton
386	135	jt_eaton
387			`fs-common`
388	131	jt_eaton
389	135	jt_eaton
390
391			`../verilog/top.body`
392			`verilogSourcefragment`
393
394	131	jt_eaton
395	135	jt_eaton
396	131	jt_eaton
397	135	jt_eaton
398			`fs-sim`
399	131	jt_eaton
400	135	jt_eaton
401
402			`../verilog/copyright.v`
403			`verilogSourceinclude`
404
405
406
407			`../verilog/common/io_ext_mem_interface_def`
408			`verilogSourcemodule`
409
410	131	jt_eaton
411
412	135	jt_eaton
413			`mb`
414			`../verilog/io_ext_mem_interface_def_mb`
415			`verilogSourcemodule`
416
417	131	jt_eaton
418
419
420	135	jt_eaton
421	131	jt_eaton
422
423
424	135	jt_eaton
425			`fs-syn`
426	131	jt_eaton
427	135	jt_eaton
428
429			`../verilog/copyright.v`
430			`verilogSourceinclude`
431
432	131	jt_eaton
433	135	jt_eaton
434
435			`../verilog/common/io_ext_mem_interface_def`
436			`verilogSourcemodule`
437
438	131	jt_eaton
439
440	135	jt_eaton
441			`mb`
442			`../verilog/io_ext_mem_interface_def_mb`
443			`verilogSourcemodule`
444
445	131	jt_eaton
446
447
448	135	jt_eaton
449	131	jt_eaton
450
451
452
453	135	jt_eaton
454	131	jt_eaton
455
456
457
458
459	135	jt_eaton
460	131	jt_eaton
461	135	jt_eaton
462
463			`Hierarchical`
464
465
466
467	131	jt_eaton
468
469
470	135	jt_eaton
471
472	131	jt_eaton
473	135	jt_eaton
474			`Hierarchical`
475			`Hierarchical`
476
477
478
479
480			`verilog`
481
482
483			`ipxact:library="Testbench"`
484			`ipxact:name="toolflow"`
485			`ipxact:version="verilog"/>`
486
487
488
489
490
491
492
493
494			`common:common:`
495	131	jt_eaton
496	135	jt_eaton	`Verilog`
497
498
499			`fs-common`
500
501
502	131	jt_eaton
503	135	jt_eaton
504			`sim:Simulation:`
505	131	jt_eaton
506	135	jt_eaton	`Verilog`
507
508
509			`fs-sim`
510
511
512	131	jt_eaton
513
514	135	jt_eaton
515			`syn:Synthesis:`
516	131	jt_eaton
517	135	jt_eaton	`Verilog`
518
519
520			`fs-syn`
521
522
523	131	jt_eaton
524
525
526	135	jt_eaton
527			`doc`
528
529
530			`ipxact:library="Testbench"`
531			`ipxact:name="toolflow"`
532			`ipxact:version="documentation"/>`
533
534			`:Documentation:`
535			`Verilog`
536
537	131	jt_eaton
538
539
540	135	jt_eaton
541	131	jt_eaton
542
543
544
545	135	jt_eaton
546	131	jt_eaton
547	135	jt_eaton	`enable`
548			`wire`
549			`in`
550
551	131	jt_eaton
552	135	jt_eaton
553			`clk`
554			`wire`
555			`in`
556
557	131	jt_eaton
558
559	135	jt_eaton	`reset`
560			`wire`
561			`in`
562
563	131	jt_eaton
564
565	135	jt_eaton	`cs`
566			`wire`
567			`in`
568
569	131	jt_eaton
570
571	135	jt_eaton	`rd`
572			`wire`
573			`in`
574
575	131	jt_eaton
576	135	jt_eaton	`wr`
577			`wire`
578			`in`
579
580	131	jt_eaton
581
582	135	jt_eaton	`addr`
583			`wire`
584			`in`
585			`30`
586
587	131	jt_eaton
588
589	135	jt_eaton	`wdata`
590			`wire`
591			`in`
592			`70`
593
594	131	jt_eaton
595
596	135	jt_eaton	`rdata`
597			`wire`
598			`out`
599			`70`
600
601	131	jt_eaton
602
603
604
605
606
607
608
609
610
611	135	jt_eaton	`wait_st`
612			`wire`
613			`out`
614			`70`
615
616	131	jt_eaton
617
618
619
620
621
622	135	jt_eaton	`bank`
623			`wire`
624			`out`
625			`70`
626
627	131	jt_eaton
628
629
630
631
632	135	jt_eaton
633	131	jt_eaton
634
635	135	jt_eaton	`mem_cs`
636			`wire`
637			`in`
638
639	131	jt_eaton
640
641	135	jt_eaton	`mem_rd`
642			`wire`
643			`in`
644
645	131	jt_eaton
646	135	jt_eaton	`mem_wr`
647			`wire`
648			`in`
649
650	131	jt_eaton
651
652	135	jt_eaton	`mem_addr`
653			`wire`
654			`in`
655			`130`
656
657	131	jt_eaton
658
659	135	jt_eaton	`mem_wdata`
660			`wire`
661			`in`
662			`150`
663
664	131	jt_eaton
665
666	135	jt_eaton	`mem_rdata`
667			`wire`
668			`out`
669			`150`
670
671	131	jt_eaton
672	135	jt_eaton
673
674
675
676
677			`ext_cs`
678			`wire`
679			`out`
680
681
682
683			`ext_rd`
684			`wire`
685			`out`
686
687
688			`ext_wr`
689			`wire`
690			`out`
691
692
693
694			`ext_addr`
695			`wire`
696			`out`
697			`230`
698
699
700
701			`ext_wdata`
702			`wire`
703			`out`
704			`150`
705
706
707
708			`ext_rdata`
709			`wire`
710			`in`
711			`150`
712
713
714
715
716
717
718
719
720
721			`ext_ub`
722			`reg`
723			`out`
724
725
726			`ext_stb`
727			`reg`
728			`out`
729
730
731
732
733			`ext_lb`
734			`reg`
735			`out`
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752			`mb`
753			`8`
754
755			`mb`
756			`0x0`
757
758			`ext_mem`
759			`0x10`
760			`8`
761
762			`bank`
763			`0x2`
764			`8`
765			`read-write`
766
767
768			`wait_st`
769			`0x0`
770			`8`
771			`read-write`
772
773
774
775
776
777
778
779
780			`mem`
781			`8`
782
783			`mem`
784			`0x0`
785
786			`mem`
787			`0x4000`
788			`16`
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805