URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_module
mouse
 

 
 slave_clk
  
 
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
 
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 

 
 

 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_module_mouse
    
  

 
 

 
 

 
   
      fs-common
 
      
        
        ../verilog/top.mouse.rtl
        verilogSourcefragment
      
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_mouse
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
   
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_module_mouse
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
 
 

 
 
 
 
 

 
                
                        
                                Hierarchical
                                
                        
                
 
 
       
 
              
              Hierarchical
               Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
 
enable
wire
in

 
 
 
 
wait_n
wire
out

 
 
gpio_0_out
wire
out
70

 
gpio_0_oe
wire
out
70

 
 
 
gpio_0_in
wire
in
70

 
gpio_1_out
wire
out
70

 
gpio_1_oe
wire
out
70

 
 
 
gpio_1_in
wire
in
70

 
timer_irq
wire
out
10

 
pic_irq
wire
out

 
pic_nmi
wire
out

 
pic_irq_in
wire
in
70

 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
wire
out

 
tx_irq
wire
out

 
ps2_data_avail
wire
out

 
y_pos
wire
out
90

 
x_pos
wire
out
90

 
new_packet
wire
out

 
ms_mid
wire
out

 
ms_right
wire
out

 
ms_left
wire
out

 
 

 
 

 
 
 


 
8
 mb

 mb
 0x00
 
  
  gpio
  0x10
  8
 
 
 
   0_out
   0x2
   8
   read-write
  
 
 
   0_oe
   0x1
   8
   read-write
  
 
 
   0_in
   0x0
   8
   read-only
  
 
 
 
   1_out
   0x6
   8
   read-write
  
 
 
   1_oe
   0x5
   8
   read-write
  
 
 
   1_in
   0x4
   8
   read-only
  
 
 
  
 
 

 

 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_module`
40			`mouse`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58
59	131	jt_eaton
60
61	135	jt_eaton	`slave_reset`
62
63
64
65
66
67
68			`reset`
69			`reset`
70
71
72
73
74
75
76	131	jt_eaton
77
78	135	jt_eaton
79	131	jt_eaton
80
81	135	jt_eaton
82	131	jt_eaton
83
84
85
86
87
88
89	135	jt_eaton
90			`gen_registers`
91			`102.1`
92			`:common:`
93			`none`
94			`tools/regtool/gen_registers`
95
96
97			`bus_intf`
98			`mb`
99
100
101			`dest_dir`
102			`../verilog`
103
104
105
106	131	jt_eaton
107
108
109	135	jt_eaton
110			`gen_verilog`
111			`104.0`
112			`none`
113			`:common:`
114			`tools/verilog/gen_verilog`
115
116
117			`destination`
118			`io_module_mouse`
119
120
121
122	131	jt_eaton
123
124	135	jt_eaton
125	131	jt_eaton
126
127	135	jt_eaton
128	131	jt_eaton
129	135	jt_eaton
130			`fs-common`
131	131	jt_eaton
132	135	jt_eaton
133
134			`../verilog/top.mouse.rtl`
135			`verilogSourcefragment`
136
137	131	jt_eaton
138	135	jt_eaton
139	131	jt_eaton
140
141	135	jt_eaton
142			`fs-sim`
143	131	jt_eaton
144	135	jt_eaton
145
146			`../verilog/copyright`
147			`verilogSourceinclude`
148
149	131	jt_eaton
150	135	jt_eaton
151
152			`../verilog/common/io_module_mouse`
153			`verilogSourcemodule`
154
155	134	jt_eaton
156
157	135	jt_eaton
158			`dest_dir`
159			`../views/sim/`
160			`verilogSourcelibraryDir`
161
162	131	jt_eaton
163
164	135	jt_eaton
165	131	jt_eaton
166
167	135	jt_eaton
168			`fs-syn`
169	131	jt_eaton
170	135	jt_eaton
171
172			`../verilog/copyright`
173			`verilogSourceinclude`
174
175	131	jt_eaton
176	135	jt_eaton
177
178			`../verilog/common/io_module_mouse`
179			`verilogSourcemodule`
180
181	131	jt_eaton
182
183	135	jt_eaton
184			`dest_dir`
185			`../views/syn/`
186			`verilogSourcelibraryDir`
187
188	131	jt_eaton
189
190
191	135	jt_eaton
192	131	jt_eaton
193
194
195
196	135	jt_eaton
197	131	jt_eaton
198	135	jt_eaton
199
200	131	jt_eaton
201
202	135	jt_eaton
203	131	jt_eaton
204	135	jt_eaton
205
206			`Hierarchical`
207
208
209
210	131	jt_eaton
211	135	jt_eaton
212
213	131	jt_eaton
214	135	jt_eaton
215			`Hierarchical`
216			`Hierarchical`
217
218	131	jt_eaton
219
220	135	jt_eaton
221			`verilog`
222
223
224			`ipxact:library="Testbench"`
225			`ipxact:name="toolflow"`
226			`ipxact:version="verilog"/>`
227
228
229	131	jt_eaton
230
231
232
233
234	135	jt_eaton
235			`common:common:`
236			`Verilog`
237
238
239			`fs-common`
240
241
242	131	jt_eaton
243	135	jt_eaton
244			`sim:Simulation:`
245			`Verilog`
246
247
248			`fs-sim`
249
250
251	131	jt_eaton
252
253	135	jt_eaton
254			`syn:Synthesis:`
255			`Verilog`
256
257
258			`fs-syn`
259
260
261	131	jt_eaton
262
263	135	jt_eaton
264			`doc`
265
266
267			`ipxact:library="Testbench"`
268			`ipxact:name="toolflow"`
269			`ipxact:version="documentation"/>`
270
271			`:Documentation:`
272			`Verilog`
273
274	131	jt_eaton
275
276
277	135	jt_eaton
278	131	jt_eaton
279
280
281
282
283
284	135	jt_eaton
285	131	jt_eaton
286
287	135	jt_eaton
288			`clk`
289			`wire`
290			`in`
291
292	131	jt_eaton
293
294	135	jt_eaton	`reset`
295			`wire`
296			`in`
297
298	131	jt_eaton
299
300
301	135	jt_eaton	`enable`
302			`wire`
303			`in`
304
305	131	jt_eaton
306
307
308
309	135	jt_eaton	`wait_n`
310			`wire`
311			`out`
312
313	131	jt_eaton
314
315	135	jt_eaton	`gpio_0_out`
316			`wire`
317			`out`
318			`70`
319
320	131	jt_eaton
321	135	jt_eaton	`gpio_0_oe`
322			`wire`
323			`out`
324			`70`
325
326	131	jt_eaton
327
328
329	135	jt_eaton	`gpio_0_in`
330			`wire`
331			`in`
332			`70`
333
334	131	jt_eaton
335	135	jt_eaton	`gpio_1_out`
336			`wire`
337			`out`
338			`70`
339
340	131	jt_eaton
341	135	jt_eaton	`gpio_1_oe`
342			`wire`
343			`out`
344			`70`
345
346	131	jt_eaton
347
348
349	135	jt_eaton	`gpio_1_in`
350			`wire`
351			`in`
352			`70`
353
354	131	jt_eaton
355	135	jt_eaton	`timer_irq`
356			`wire`
357			`out`
358			`10`
359
360	131	jt_eaton
361	135	jt_eaton	`pic_irq`
362			`wire`
363			`out`
364
365	131	jt_eaton
366	135	jt_eaton	`pic_nmi`
367			`wire`
368			`out`
369
370	131	jt_eaton
371	135	jt_eaton	`pic_irq_in`
372			`wire`
373			`in`
374			`70`
375
376	131	jt_eaton
377
378	135	jt_eaton	`cts_pad_in`
379			`wire`
380			`in`
381
382	131	jt_eaton
383	135	jt_eaton	`rts_pad_out`
384			`wire`
385			`out`
386
387	131	jt_eaton
388	135	jt_eaton	`rx_irq`
389			`wire`
390			`out`
391
392	131	jt_eaton
393	135	jt_eaton	`tx_irq`
394			`wire`
395			`out`
396
397	131	jt_eaton
398	135	jt_eaton	`ps2_data_avail`
399			`wire`
400			`out`
401
402	131	jt_eaton
403	135	jt_eaton	`y_pos`
404			`wire`
405			`out`
406			`90`
407
408	131	jt_eaton
409	135	jt_eaton	`x_pos`
410			`wire`
411			`out`
412			`90`
413
414	131	jt_eaton
415	135	jt_eaton	`new_packet`
416			`wire`
417			`out`
418
419	131	jt_eaton
420	135	jt_eaton	`ms_mid`
421			`wire`
422			`out`
423
424	131	jt_eaton
425	135	jt_eaton	`ms_right`
426			`wire`
427			`out`
428
429	131	jt_eaton
430	135	jt_eaton	`ms_left`
431			`wire`
432			`out`
433
434	131	jt_eaton
435
436	135	jt_eaton
437
438
439
440
441
442
443
444
445
446			`8`
447			`mb`
448
449			`mb`
450			`0x00`
451	131	jt_eaton
452	135	jt_eaton
453			`gpio`
454			`0x10`
455			`8`
456	131	jt_eaton
457
458	135	jt_eaton
459			`0_out`
460			`0x2`
461			`8`
462			`read-write`
463
464	131	jt_eaton
465	135	jt_eaton
466			`0_oe`
467			`0x1`
468			`8`
469			`read-write`
470
471	131	jt_eaton
472	135	jt_eaton
473			`0_in`
474			`0x0`
475			`8`
476			`read-only`
477
478	131	jt_eaton
479
480	135	jt_eaton
481			`1_out`
482			`0x6`
483			`8`
484			`read-write`
485
486	131	jt_eaton
487	135	jt_eaton
488			`1_oe`
489			`0x5`
490			`8`
491			`read-write`
492
493	131	jt_eaton
494	135	jt_eaton
495			`1_in`
496			`0x4`
497			`8`
498			`read-only`
499
500	131	jt_eaton
501
502	135	jt_eaton
503	131	jt_eaton
504
505	135	jt_eaton
506	131	jt_eaton
507	135	jt_eaton
508	131	jt_eaton
509
510
511	135	jt_eaton
512	131	jt_eaton
513
514
515
516

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_mouse.xml] - Blame information for rev 135