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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_ps2
def
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  

      
  
    
      
        reset
        reset
      
    
      
      
  
 
 
 
mb
   

      
   
     
        
         rdata
         
         rdata
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
 
        
      
 
   little
   8
     
  
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_ps2_def
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_ps2_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_ps2_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
       
 
              
              Hierarchical
               Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
rcv_data_avail
wire
out

 
 
 
 

 

 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_ps2`
40			`def`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79	135	jt_eaton	`mb`
80
81
82
83
84
85
86			`rdata`
87
88			`rdata`
89			`70`
90
91
92	131	jt_eaton
93	135	jt_eaton
94			`addr`
95
96			`addr`
97			`30`
98
99
100	131	jt_eaton
101
102	135	jt_eaton
103			`wdata`
104
105			`wdata`
106			`70`
107
108
109	131	jt_eaton
110
111	135	jt_eaton
112			`rd`
113
114			`rd`
115
116
117	131	jt_eaton
118	135	jt_eaton
119			`wr`
120
121			`wr`
122
123
124	131	jt_eaton
125	135	jt_eaton
126			`cs`
127
128			`cs`
129
130
131	131	jt_eaton
132	135	jt_eaton
133	131	jt_eaton
134	135	jt_eaton
135
136	131	jt_eaton
137	135	jt_eaton	`little`
138			`8`
139
140
141	131	jt_eaton
142
143	135	jt_eaton
144	131	jt_eaton
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151
152
153
154	135	jt_eaton
155			`gen_registers`
156			`102.1`
157			`:common:`
158			`none`
159			`tools/regtool/gen_registers`
160
161
162			`bus_intf`
163			`mb`
164
165
166			`dest_dir`
167			`../verilog`
168
169
170
171	131	jt_eaton
172
173
174	135	jt_eaton
175			`gen_verilog`
176			`104.0`
177			`none`
178			`:common:`
179			`tools/verilog/gen_verilog`
180
181
182			`destination`
183			`io_ps2_def`
184
185
186
187	131	jt_eaton
188
189
190	135	jt_eaton
191	131	jt_eaton
192
193
194	135	jt_eaton
195	131	jt_eaton
196	135	jt_eaton
197			`fs-common`
198	131	jt_eaton
199	135	jt_eaton
200
201			`../verilog/top.body`
202			`verilogSourcefragment`
203
204	131	jt_eaton
205	135	jt_eaton
206	131	jt_eaton
207
208	135	jt_eaton
209			`fs-sim`
210	131	jt_eaton
211	135	jt_eaton
212
213			`../verilog/copyright.v`
214			`verilogSourceinclude`
215
216	131	jt_eaton
217	135	jt_eaton
218
219			`../verilog/common/io_ps2_def`
220			`verilogSourcemodule`
221
222	131	jt_eaton
223	135	jt_eaton
224			`mb`
225			`../verilog/io_ps2_def_mb`
226			`verilogSourcemodule`
227
228	131	jt_eaton
229
230
231	135	jt_eaton
232	131	jt_eaton
233
234
235	135	jt_eaton
236			`fs-syn`
237	131	jt_eaton
238
239	135	jt_eaton
240
241			`../verilog/copyright.v`
242			`verilogSourceinclude`
243
244	131	jt_eaton
245	135	jt_eaton
246
247			`../verilog/common/io_ps2_def`
248			`verilogSourcemodule`
249
250	131	jt_eaton
251	135	jt_eaton
252			`mb`
253			`../verilog/io_ps2_def_mb`
254			`verilogSourcemodule`
255
256	131	jt_eaton
257
258
259
260
261	135	jt_eaton
262	131	jt_eaton
263
264
265
266	135	jt_eaton
267	131	jt_eaton
268
269
270
271
272	135	jt_eaton
273	131	jt_eaton
274
275	135	jt_eaton
276
277			`Hierarchical`
278
279
280
281	131	jt_eaton
282
283	135	jt_eaton
284
285
286	131	jt_eaton
287	135	jt_eaton
288			`Hierarchical`
289			`Hierarchical`
290	131	jt_eaton
291	135	jt_eaton
292	131	jt_eaton
293
294	135	jt_eaton
295			`verilog`
296
297
298			`ipxact:library="Testbench"`
299			`ipxact:name="toolflow"`
300			`ipxact:version="verilog"/>`
301
302
303	131	jt_eaton
304
305
306
307
308	135	jt_eaton
309			`common:common:`
310			`Verilog`
311
312
313			`fs-common`
314
315
316	131	jt_eaton
317	135	jt_eaton
318			`sim:Simulation:`
319			`Verilog`
320
321
322			`fs-sim`
323
324
325	131	jt_eaton
326
327	135	jt_eaton
328			`syn:Synthesis:`
329			`Verilog`
330
331
332			`fs-syn`
333
334
335	131	jt_eaton
336
337	135	jt_eaton
338			`doc`
339
340
341			`ipxact:library="Testbench"`
342			`ipxact:name="toolflow"`
343			`ipxact:version="documentation"/>`
344
345			`:Documentation:`
346			`Verilog`
347
348	131	jt_eaton
349
350
351	135	jt_eaton
352	131	jt_eaton
353
354
355
356
357	135	jt_eaton
358	131	jt_eaton
359
360	135	jt_eaton	`enable`
361			`wire`
362			`in`
363
364	131	jt_eaton
365	135	jt_eaton
366			`clk`
367			`wire`
368			`in`
369
370	131	jt_eaton
371
372	135	jt_eaton	`reset`
373			`wire`
374			`in`
375
376	131	jt_eaton
377
378	135	jt_eaton	`cs`
379			`wire`
380			`in`
381
382
383
384			`rd`
385			`wire`
386			`in`
387
388
389			`wr`
390			`wire`
391			`in`
392
393
394
395			`addr`
396			`wire`
397			`in`
398			`30`
399
400
401
402			`wdata`
403			`wire`
404			`in`
405			`70`
406
407
408
409			`rdata`
410			`wire`
411			`out`
412			`70`
413
414
415
416
417
418			`rcv_data_avail`
419			`wire`
420			`out`
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435			`mb`
436			`8`
437
438			`mb`
439			`0x00`
440	131	jt_eaton
441	135	jt_eaton
442			`mb_microbus`
443			`0x10`
444			`8`
445	131	jt_eaton
446
447	135	jt_eaton
448			`ps2_data`
449			`0x0`
450			`8`
451			`read-only`
452
453	131	jt_eaton
454	135	jt_eaton
455			`wdata_buf`
456			`0x0`
457			`8`
458			`write-only`
459
460	131	jt_eaton
461	135	jt_eaton
462			`status`
463			`0x2`
464			`8`
465			`read-only`
466
467	131	jt_eaton
468	135	jt_eaton
469			`cntrl`
470			`0x4`
471			`8`
472			`read-write`
473
474	131	jt_eaton
475
476
477
478	135	jt_eaton
479	131	jt_eaton
480
481	135	jt_eaton
482	131	jt_eaton
483	135	jt_eaton
484	131	jt_eaton
485
486
487	135	jt_eaton