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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_ps2
mouse
 
 

 
 slave_clk
  
  
      
      
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
      
      
  
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
        
      
 
 
   little
   8
     
 
  
 
 

 
 
 

 
 
 
 

  gen_registers
  102.1
  none
  :*common:*
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  verilog_maker
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_ps2_mouse
    
  

 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body.mouse
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_ps2_mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_ps2_mouse
        verilogSourcemodule
      
 
      
        micro_reg
        ../verilog/io_ps2_mouse_micro_reg
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
  
 
 
 
 
 
  
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
              
              Hierarchical
                  Hierarchical
 
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
rcv_data_avail
wire
out

 
y_pos
reg
out
90

 
x_pos
reg
out
90

 
new_packet
reg
out

 
ms_mid
reg
out

 
ms_right
reg
out

 
ms_left
reg
out

 

 

 
 
 


 mb
8

 micro_reg
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
   x_pos
   0x6
   8
   read-only
  
 
 
   y_pos
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_mouse.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_ps2`
40			`mouse`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79	135	jt_eaton	`mb`
80
81
82
83
84
85
86			`rdata`
87
88			`rdata`
89			`70`
90
91
92	131	jt_eaton
93	135	jt_eaton
94			`addr`
95
96			`addr`
97			`30`
98
99
100	131	jt_eaton
101
102	135	jt_eaton
103			`wdata`
104
105			`wdata`
106			`70`
107
108
109	131	jt_eaton
110
111	135	jt_eaton
112			`rd`
113
114			`rd`
115
116
117	131	jt_eaton
118	135	jt_eaton
119			`wr`
120
121			`wr`
122
123
124	131	jt_eaton
125	135	jt_eaton
126			`cs`
127
128			`cs`
129
130
131	131	jt_eaton
132	135	jt_eaton
133
134
135	131	jt_eaton
136
137	135	jt_eaton	`little`
138			`8`
139
140	131	jt_eaton
141	135	jt_eaton
142	131	jt_eaton
143
144	135	jt_eaton
145	131	jt_eaton
146
147
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153	135	jt_eaton
154			`gen_registers`
155			`102.1`
156			`none`
157			`:common:`
158			`tools/regtool/gen_registers`
159
160
161			`bus_intf`
162			`mb`
163
164
165			`dest_dir`
166			`../verilog`
167
168
169
170	131	jt_eaton
171
172
173	135	jt_eaton
174			`verilog_maker`
175			`104.0`
176			`none`
177			`:common:`
178			`tools/verilog/gen_verilog`
179
180
181			`destination`
182			`io_ps2_mouse`
183
184
185
186	131	jt_eaton
187
188	135	jt_eaton
189	131	jt_eaton
190
191
192	135	jt_eaton
193	131	jt_eaton
194	135	jt_eaton
195			`fs-common`
196	131	jt_eaton
197	135	jt_eaton
198
199			`../verilog/top.body.mouse`
200			`verilogSourcefragment`
201
202	131	jt_eaton
203	135	jt_eaton
204	131	jt_eaton
205
206	135	jt_eaton
207			`fs-sim`
208	131	jt_eaton
209
210	135	jt_eaton
211
212			`../verilog/copyright.v`
213			`verilogSourceinclude`
214
215	131	jt_eaton
216	135	jt_eaton
217
218			`../verilog/common/io_ps2_mouse`
219			`verilogSourcemodule`
220
221	131	jt_eaton
222	135	jt_eaton
223			`micro_reg`
224			`../verilog/io_ps2_mouse_micro_reg`
225			`verilogSourcemodule`
226
227	131	jt_eaton
228
229
230
231	135	jt_eaton
232	131	jt_eaton
233
234
235
236	135	jt_eaton
237			`fs-syn`
238	131	jt_eaton
239
240
241	135	jt_eaton
242
243			`../verilog/copyright.v`
244			`verilogSourceinclude`
245
246	131	jt_eaton
247	135	jt_eaton
248
249			`../verilog/common/io_ps2_mouse`
250			`verilogSourcemodule`
251
252	131	jt_eaton
253	135	jt_eaton
254			`micro_reg`
255			`../verilog/io_ps2_mouse_micro_reg`
256			`verilogSourcemodule`
257
258	131	jt_eaton
259
260
261
262	135	jt_eaton
263	131	jt_eaton
264
265
266	135	jt_eaton
267	131	jt_eaton
268
269
270
271
272	135	jt_eaton
273	131	jt_eaton
274	135	jt_eaton
275
276			`Hierarchical`
277
278
279
280	131	jt_eaton
281
282	135	jt_eaton
283
284	131	jt_eaton
285	135	jt_eaton
286			`Hierarchical`
287			`Hierarchical`
288	131	jt_eaton
289	135	jt_eaton
290	131	jt_eaton
291	135	jt_eaton
292			`verilog`
293
294
295			`ipxact:library="Testbench"`
296			`ipxact:name="toolflow"`
297			`ipxact:version="verilog"/>`
298
299
300	131	jt_eaton
301
302
303
304
305	135	jt_eaton
306			`common:common:`
307			`Verilog`
308
309
310			`fs-common`
311
312
313	131	jt_eaton
314	135	jt_eaton
315			`sim:Simulation:`
316			`Verilog`
317
318
319			`fs-sim`
320
321
322	131	jt_eaton
323
324	135	jt_eaton
325			`syn:Synthesis:`
326			`Verilog`
327
328
329			`fs-syn`
330
331
332	131	jt_eaton
333
334	135	jt_eaton
335			`doc`
336
337
338			`ipxact:library="Testbench"`
339			`ipxact:name="toolflow"`
340			`ipxact:version="documentation"/>`
341
342			`:Documentation:`
343			`Verilog`
344
345	131	jt_eaton
346
347
348	135	jt_eaton
349	131	jt_eaton
350
351
352
353
354	135	jt_eaton
355	131	jt_eaton
356
357	135	jt_eaton	`enable`
358			`wire`
359			`in`
360
361	131	jt_eaton
362	135	jt_eaton
363			`clk`
364			`wire`
365			`in`
366
367	131	jt_eaton
368
369	135	jt_eaton	`reset`
370			`wire`
371			`in`
372
373	131	jt_eaton
374
375	135	jt_eaton	`cs`
376			`wire`
377			`in`
378
379	131	jt_eaton
380
381	135	jt_eaton	`rd`
382			`wire`
383			`in`
384
385
386			`wr`
387			`wire`
388			`in`
389
390
391
392			`addr`
393			`wire`
394			`in`
395			`30`
396
397
398
399			`wdata`
400			`wire`
401			`in`
402			`70`
403
404
405
406			`rdata`
407			`wire`
408			`out`
409			`70`
410
411
412
413
414
415			`rcv_data_avail`
416			`wire`
417			`out`
418
419
420			`y_pos`
421			`reg`
422			`out`
423			`90`
424
425
426			`x_pos`
427			`reg`
428			`out`
429			`90`
430
431
432			`new_packet`
433			`reg`
434			`out`
435
436
437			`ms_mid`
438			`reg`
439			`out`
440
441
442			`ms_right`
443			`reg`
444			`out`
445
446
447			`ms_left`
448			`reg`
449			`out`
450
451
452
453
454
455
456
457
458
459
460			`mb`
461			`8`
462
463			`micro_reg`
464			`0x00`
465	131	jt_eaton
466	135	jt_eaton
467			`mb_microbus`
468			`0x10`
469			`8`
470	131	jt_eaton
471
472	135	jt_eaton
473			`ps2_data`
474			`0x0`
475			`8`
476			`read-only`
477
478	131	jt_eaton
479
480	135	jt_eaton
481			`wdata_buf`
482			`0x0`
483			`8`
484			`write-only`
485
486	131	jt_eaton
487
488	135	jt_eaton
489			`status`
490			`0x2`
491			`8`
492			`read-only`
493
494	131	jt_eaton
495	135	jt_eaton
496			`cntrl`
497			`0x4`
498			`8`
499			`read-write`
500
501	131	jt_eaton
502
503	135	jt_eaton
504			`x_pos`
505			`0x6`
506			`8`
507			`read-only`
508
509	131	jt_eaton
510	135	jt_eaton
511			`y_pos`
512			`0x8`
513			`8`
514			`read-only`
515
516	131	jt_eaton
517
518	135	jt_eaton
519	131	jt_eaton
520
521	135	jt_eaton
522	131	jt_eaton
523	135	jt_eaton
524	131	jt_eaton
525
526
527	135	jt_eaton