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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_ps2
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_ps2_def_tb
    
  

 
 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4
    addr_width4
    PS2_MODEL_CLKCNT8'h7f
    PS2_MODEL_SIZE8

 
       
 
 
              
              Params
              
              
                                   ipxact:library="io"
                                   ipxact:name="io_ps2"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
 
              
              Bfm
              
                                   ipxact:library="io"
                                   ipxact:name="io_ps2"
                                   ipxact:version="bfm.design"/>
              
 
 
 
 
 
              
              Ps2_bfm
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="ps2_model"
                                   ipxact:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              headersheaders
                            Verilog
              
              
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/io_ps2_def_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/io_ps2_def_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [sim/] [testbenches/] [xml/] [io_ps2_def_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_ps2`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51
52	135	jt_eaton
53			`gen_verilog`
54			`104.0`
55			`none`
56			`:common:`
57			`tools/verilog/gen_verilog`
58
59
60			`destination`
61			`io_ps2_def_tb`
62
63
64
65	131	jt_eaton
66
67
68	135	jt_eaton
69	131	jt_eaton
70
71
72
73
74	135	jt_eaton
75
76			`BUS_ADDR_WIDTH4`
77			`addr_width4`
78			`PS2_MODEL_CLKCNT8'h7f`
79			`PS2_MODEL_SIZE8`
80
81	131	jt_eaton
82	135	jt_eaton
83	131	jt_eaton
84
85	135	jt_eaton
86			`Params`
87
88
89			`ipxact:library="io"`
90			`ipxact:name="io_ps2"`
91			`ipxact:version="def_dut.params"/>`
92
93
94	131	jt_eaton
95
96
97	135	jt_eaton
98			`Bfm`
99
100			`ipxact:library="io"`
101			`ipxact:name="io_ps2"`
102			`ipxact:version="bfm.design"/>`
103
104	131	jt_eaton
105
106
107
108
109	135	jt_eaton
110			`Ps2_bfm`
111
112
113			`ipxact:library="Testbench"`
114			`ipxact:name="ps2_model"`
115			`ipxact:version="bfm"/>`
116
117
118	131	jt_eaton
119
120
121
122
123
124
125	135	jt_eaton
126			`icarus`
127
128
129			`ipxact:library="Testbench"`
130			`ipxact:name="toolflow"`
131			`ipxact:version="icarus"/>`
132
133
134	131	jt_eaton
135
136
137
138
139	135	jt_eaton
140			`headersheaders`
141			`Verilog`
142
143
144	131	jt_eaton
145	135	jt_eaton
146			`common:common:`
147			`Verilog`
148
149
150			`fs-common`
151
152
153	131	jt_eaton
154	135	jt_eaton
155			`sim:Simulation:`
156			`Verilog`
157
158
159			`fs-sim`
160
161
162	131	jt_eaton
163
164
165	135	jt_eaton
166			`lint:Lint:`
167			`Verilog`
168
169
170			`fs-lint`
171
172
173	131	jt_eaton
174	135	jt_eaton
175	131	jt_eaton
176
177
178	135	jt_eaton
179	131	jt_eaton
180
181
182
183	135	jt_eaton
184	131	jt_eaton
185	135	jt_eaton
186			`fs-common`
187	131	jt_eaton
188	135	jt_eaton
189
190			`../verilog/tb.ext`
191			`verilogSourcefragment`
192
193	131	jt_eaton
194
195	135	jt_eaton
196	131	jt_eaton
197
198	135	jt_eaton
199			`fs-sim`
200	131	jt_eaton
201	135	jt_eaton
202
203			`../verilog/common/io_ps2_def_tb`
204			`verilogSourcemodule`
205
206	131	jt_eaton
207	135	jt_eaton
208	131	jt_eaton
209
210	135	jt_eaton
211			`fs-lint`
212	131	jt_eaton
213	135	jt_eaton
214
215			`../verilog/common/io_ps2_def_tb`
216			`verilogSourcemodule`
217
218	131	jt_eaton
219
220
221
222
223
224	135	jt_eaton
225	131	jt_eaton
226
227
228
229
230
231	135	jt_eaton
232	131	jt_eaton
233
234
235	135	jt_eaton