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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rx.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
rx
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
 
        
      
 
   little
   8
     
  
 
 
 

 
 
 

 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
   
    
      destination
      io_uart_rx
    
  

 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_uart_rx
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_uart_rx_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
       
 
              
              Hierarchical
                  Hierarchical
 
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
rx_irq
reg
out

 
tx_irq
reg
out

 

 

 
 
 
 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   xmit_data
   0x0
   8
   write-only
  
 
 
   rcv_data
   0x2
   8
   read-only
  
 
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
   status
   0x6
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [rtl/] [xml/] [io_uart_rx.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`rx`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80
81	135	jt_eaton	`mb`
82
83
84
85
86
87
88			`rdata`
89
90			`rdata`
91			`wire`
92			`70`
93
94
95	131	jt_eaton
96	135	jt_eaton
97			`addr`
98
99			`addr`
100			`30`
101
102
103	131	jt_eaton
104	135	jt_eaton
105			`wdata`
106
107			`wdata`
108			`70`
109
110
111	131	jt_eaton
112
113	135	jt_eaton
114			`rd`
115
116			`rd`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`wr`
122
123			`wr`
124
125
126	131	jt_eaton
127	135	jt_eaton
128			`cs`
129
130			`cs`
131
132
133	131	jt_eaton
134	135	jt_eaton
135	131	jt_eaton
136	135	jt_eaton
137
138	131	jt_eaton
139	135	jt_eaton	`little`
140			`8`
141
142
143	131	jt_eaton
144
145
146	135	jt_eaton
147	131	jt_eaton
148
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156	135	jt_eaton
157			`gen_registers`
158			`102.1`
159			`:common:`
160			`none`
161			`tools/regtool/gen_registers`
162
163
164			`bus_intf`
165			`mb`
166
167
168			`dest_dir`
169			`../verilog`
170
171
172
173	131	jt_eaton
174	135	jt_eaton
175			`gen_verilog`
176			`104.0`
177			`none`
178			`:common:`
179			`tools/verilog/gen_verilog`
180
181
182			`destination`
183			`io_uart_rx`
184
185
186
187	131	jt_eaton
188
189
190
191	135	jt_eaton
192	131	jt_eaton
193
194
195	135	jt_eaton
196	131	jt_eaton
197	135	jt_eaton
198			`fs-common`
199	131	jt_eaton
200	135	jt_eaton
201
202			`../verilog/top.body`
203			`verilogSourcefragment`
204
205	131	jt_eaton
206
207	135	jt_eaton
208	131	jt_eaton
209	135	jt_eaton
210			`fs-sim`
211	131	jt_eaton
212	135	jt_eaton
213
214			`../verilog/copyright.v`
215			`verilogSourceinclude`
216
217	131	jt_eaton
218	135	jt_eaton
219
220			`../verilog/common/io_uart_rx`
221			`verilogSourcemodule`
222
223	131	jt_eaton
224	135	jt_eaton
225			`mb`
226			`../verilog/io_uart_rx_mb`
227			`verilogSourcemodule`
228
229	131	jt_eaton
230
231
232	135	jt_eaton
233	131	jt_eaton
234
235
236
237
238
239	135	jt_eaton
240	131	jt_eaton
241
242
243
244	135	jt_eaton
245	131	jt_eaton
246
247	135	jt_eaton
248
249			`Hierarchical`
250
251
252
253	131	jt_eaton
254
255	135	jt_eaton
256
257	131	jt_eaton
258	135	jt_eaton
259			`Hierarchical`
260			`Hierarchical`
261	131	jt_eaton
262	135	jt_eaton
263	131	jt_eaton
264	135	jt_eaton
265			`verilog`
266
267
268			`ipxact:library="Testbench"`
269			`ipxact:name="toolflow"`
270			`ipxact:version="verilog"/>`
271
272
273	131	jt_eaton
274
275
276
277
278	135	jt_eaton
279			`common:common:`
280			`Verilog`
281
282
283			`fs-common`
284
285
286	131	jt_eaton
287	135	jt_eaton
288			`sim:Simulation:`
289			`Verilog`
290
291
292			`fs-sim`
293
294
295	131	jt_eaton
296	135	jt_eaton
297			`syn:Synthesis:`
298			`Verilog`
299
300
301			`fs-sim`
302
303
304	131	jt_eaton
305
306
307	135	jt_eaton
308			`doc`
309
310
311			`ipxact:library="Testbench"`
312			`ipxact:name="toolflow"`
313			`ipxact:version="documentation"/>`
314
315			`:Documentation:`
316			`Verilog`
317
318	131	jt_eaton
319
320
321
322	135	jt_eaton
323	131	jt_eaton
324
325
326	135	jt_eaton
327	131	jt_eaton
328
329	135	jt_eaton	`enable`
330			`wire`
331			`in`
332
333	131	jt_eaton
334
335	135	jt_eaton
336			`clk`
337			`wire`
338			`in`
339
340	131	jt_eaton
341
342	135	jt_eaton	`reset`
343			`wire`
344			`in`
345
346	131	jt_eaton
347
348	135	jt_eaton	`cs`
349			`wire`
350			`in`
351
352	131	jt_eaton
353
354	135	jt_eaton	`rd`
355			`wire`
356			`in`
357
358	131	jt_eaton
359	135	jt_eaton	`wr`
360			`wire`
361			`in`
362
363	131	jt_eaton
364
365	135	jt_eaton	`addr`
366			`wire`
367			`in`
368			`30`
369
370	131	jt_eaton
371	135	jt_eaton
372			`wdata`
373			`wire`
374			`in`
375			`70`
376
377
378
379			`rdata`
380			`wire`
381			`out`
382			`70`
383
384
385
386
387
388
389			`cts_pad_in`
390			`wire`
391			`in`
392
393
394			`rts_pad_out`
395			`wire`
396			`out`
397
398
399			`rx_irq`
400			`reg`
401			`out`
402
403
404			`tx_irq`
405			`reg`
406			`out`
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421			`mb`
422			`8`
423
424			`mb`
425			`0x00`
426	131	jt_eaton
427	135	jt_eaton
428			`mb_microbus`
429			`0x10`
430			`8`
431	131	jt_eaton
432
433	135	jt_eaton
434			`xmit_data`
435			`0x0`
436			`8`
437			`write-only`
438
439	131	jt_eaton
440	135	jt_eaton
441			`rcv_data`
442			`0x2`
443			`8`
444			`read-only`
445
446	131	jt_eaton
447
448	135	jt_eaton
449			`cntrl`
450			`0x4`
451			`8`
452			`read-write`
453
454	131	jt_eaton
455	135	jt_eaton
456			`status`
457			`0x6`
458			`8`
459			`read-only`
460
461	131	jt_eaton
462
463	135	jt_eaton
464	131	jt_eaton
465
466	135	jt_eaton
467	131	jt_eaton
468	135	jt_eaton
469	131	jt_eaton
470
471
472
473	135	jt_eaton