URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_def_lint.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_uart
def_lint
 
 
 
 
 
 

 

    BUS_ADDR_WIDTH4
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
       
 
              
              Dut
              
              
                                   ipxact:library="io"
                                   ipxact:name="io_uart"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
 
 
      
 
 
 
 

 
 
 
 
  
 
 
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/io_uart_def_lint
        verilogSource
        module
      
 
 
    
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_uart`
40			`def_lint`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49	135	jt_eaton
50			`BUS_ADDR_WIDTH4`
51			`UART_MODEL_CLKCNT4'b1100`
52			`UART_MODEL_SIZE4`
53
54	131	jt_eaton
55
56	135	jt_eaton
57	131	jt_eaton
58	135	jt_eaton
59			`Dut`
60
61
62			`ipxact:library="io"`
63			`ipxact:name="io_uart"`
64			`ipxact:version="def_dut.params"/>`
65
66
67	131	jt_eaton
68
69	135	jt_eaton
70			`lint`
71			`:Lint:`
72			`Verilog`
73			`fs-lint`
74
75	131	jt_eaton
76
77	135	jt_eaton
78			`rtl_check`
79
80
81			`ipxact:library="Testbench"`
82			`ipxact:name="toolflow"`
83			`ipxact:version="rtl_check"/>`
84
85
86	131	jt_eaton
87
88
89	135	jt_eaton
90	131	jt_eaton
91
92
93
94	135	jt_eaton
95	131	jt_eaton
96
97
98
99	135	jt_eaton
100	131	jt_eaton
101
102
103
104
105
106	135	jt_eaton
107			`fs-lint`
108	131	jt_eaton
109	135	jt_eaton
110
111			`../verilog/lint/io_uart_def_lint`
112			`verilogSource`
113			`module`
114
115	131	jt_eaton
116
117	135	jt_eaton
118	131	jt_eaton
119
120
121
122	135	jt_eaton
123	131	jt_eaton
124
125
126	135	jt_eaton

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_uart/] [sim/] [testbenches/] [xml/] [io_uart_def_lint.xml] - Blame information for rev 135