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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_vic
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
 
        
      
   little
   8
     
  
 
 

 
 

 
 
 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      io_vic_def
    
  

 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_vic_def
        verilogSourcemodule
      
 
 
    
        mb
        ../verilog/io_vic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
  
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
       
 
              
              Hierarchical
                  Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
int_in
wire
in
70

 
irq_out
reg
out

 
vector
reg
out
70

 


 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   irq_vec
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_vic`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76
77
78	131	jt_eaton
79
80	135	jt_eaton	`mb`
81
82
83
84
85
86
87			`rdata`
88
89			`rdata`
90			`wire`
91			`70`
92
93
94	131	jt_eaton
95	135	jt_eaton
96			`addr`
97
98			`addr`
99			`30`
100
101
102	131	jt_eaton
103	135	jt_eaton
104			`wdata`
105
106			`wdata`
107			`70`
108
109
110	131	jt_eaton
111
112	135	jt_eaton
113			`rd`
114
115			`rd`
116
117
118	131	jt_eaton
119	135	jt_eaton
120			`wr`
121
122			`wr`
123
124
125	131	jt_eaton
126	135	jt_eaton
127			`cs`
128
129			`cs`
130
131
132	131	jt_eaton
133	135	jt_eaton
134	131	jt_eaton
135	135	jt_eaton
136
137			`little`
138			`8`
139
140
141	131	jt_eaton
142
143	135	jt_eaton
144	131	jt_eaton
145
146	135	jt_eaton
147	131	jt_eaton
148
149
150
151
152
153	133	jt_eaton
154	131	jt_eaton
155	135	jt_eaton
156			`gen_registers`
157			`102.1`
158			`:common:`
159			`none`
160			`tools/regtool/gen_registers`
161
162
163			`bus_intf`
164			`mb`
165
166
167			`dest_dir`
168			`../verilog`
169
170
171
172	131	jt_eaton
173
174	135	jt_eaton
175			`gen_verilog`
176			`104.0`
177			`none`
178			`:common:`
179			`tools/verilog/gen_verilog`
180
181
182			`destination`
183			`io_vic_def`
184
185
186
187	131	jt_eaton
188
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196	135	jt_eaton
197	131	jt_eaton
198	135	jt_eaton
199			`fs-common`
200	131	jt_eaton
201	135	jt_eaton
202
203			`../verilog/top.body`
204			`verilogSourcefragment`
205
206	131	jt_eaton
207
208	135	jt_eaton
209	131	jt_eaton
210
211	135	jt_eaton
212			`fs-sim`
213	131	jt_eaton
214	135	jt_eaton
215
216			`../verilog/copyright.v`
217			`verilogSourceinclude`
218
219	131	jt_eaton
220	135	jt_eaton
221
222			`../verilog/common/io_vic_def`
223			`verilogSourcemodule`
224
225	131	jt_eaton
226
227	135	jt_eaton
228			`mb`
229			`../verilog/io_vic_def_mb`
230			`verilogSourcemodule`
231
232	131	jt_eaton
233
234
235	135	jt_eaton
236	131	jt_eaton
237
238
239
240
241	135	jt_eaton
242	131	jt_eaton
243
244
245
246
247	135	jt_eaton
248	131	jt_eaton
249	135	jt_eaton
250
251
252			`Hierarchical`
253
254
255
256	131	jt_eaton
257
258	135	jt_eaton
259	131	jt_eaton
260	135	jt_eaton
261			`Hierarchical`
262			`Hierarchical`
263	131	jt_eaton
264	135	jt_eaton
265	131	jt_eaton
266
267	135	jt_eaton
268			`verilog`
269
270
271			`ipxact:library="Testbench"`
272			`ipxact:name="toolflow"`
273			`ipxact:version="verilog"/>`
274
275
276
277
278
279
280
281
282			`common:common:`
283	131	jt_eaton
284	135	jt_eaton	`Verilog`
285
286
287			`fs-common`
288
289
290	131	jt_eaton
291	135	jt_eaton
292			`sim:Simulation:`
293	131	jt_eaton
294	135	jt_eaton	`Verilog`
295
296
297			`fs-sim`
298
299
300	131	jt_eaton
301	135	jt_eaton
302			`syn:Synthesis:`
303	131	jt_eaton
304	135	jt_eaton	`Verilog`
305
306
307			`fs-sim`
308
309
310	131	jt_eaton
311
312
313	135	jt_eaton
314			`doc`
315
316
317			`ipxact:library="Testbench"`
318			`ipxact:name="toolflow"`
319			`ipxact:version="documentation"/>`
320
321			`:Documentation:`
322			`Verilog`
323
324	131	jt_eaton
325
326
327	135	jt_eaton
328	131	jt_eaton
329
330	135	jt_eaton
331	131	jt_eaton
332
333	135	jt_eaton	`enable`
334			`wire`
335			`in`
336
337	131	jt_eaton
338
339	135	jt_eaton
340			`clk`
341			`wire`
342			`in`
343
344	131	jt_eaton
345
346	135	jt_eaton	`reset`
347			`wire`
348			`in`
349
350	131	jt_eaton
351
352	135	jt_eaton	`cs`
353			`wire`
354			`in`
355
356	131	jt_eaton
357
358	135	jt_eaton	`rd`
359			`wire`
360			`in`
361
362	131	jt_eaton
363	135	jt_eaton	`wr`
364			`wire`
365			`in`
366
367	131	jt_eaton
368	135	jt_eaton
369			`addr`
370			`wire`
371			`in`
372			`30`
373
374
375
376			`wdata`
377			`wire`
378			`in`
379			`70`
380
381
382
383			`rdata`
384			`wire`
385			`out`
386			`70`
387
388
389
390
391
392
393			`int_in`
394			`wire`
395			`in`
396			`70`
397
398
399			`irq_out`
400			`reg`
401			`out`
402
403
404			`vector`
405			`reg`
406			`out`
407			`70`
408
409
410
411
412
413
414
415
416
417			`mb`
418			`8`
419
420			`mb`
421			`0x00`
422	131	jt_eaton
423	135	jt_eaton
424			`mb_microbus`
425			`0x10`
426			`8`
427	131	jt_eaton
428
429	135	jt_eaton
430			`int_in`
431			`0x0`
432			`8`
433			`read-only`
434
435	131	jt_eaton
436	135	jt_eaton
437			`irq_enable`
438			`0x2`
439			`8`
440			`read-write`
441
442	131	jt_eaton
443
444	135	jt_eaton
445			`irq_act`
446			`0x6`
447			`8`
448			`read-only`
449
450	131	jt_eaton
451	135	jt_eaton
452			`irq_vec`
453			`0x8`
454			`8`
455			`read-only`
456
457	131	jt_eaton
458
459	135	jt_eaton
460	131	jt_eaton
461
462	135	jt_eaton
463	131	jt_eaton
464	135	jt_eaton
465	131	jt_eaton
466
467
468
469
470
471	135	jt_eaton