URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [disp_io_def.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20100214 1`
2			`C 1700 300 1 0 0 in_port_vector.sym`
3			`{`
4			`T 1700 300 5 10 1 1 0 6 1 1`
5			`refdes=sw_pad_in[7:0]`
6			`}`
7			`C 1700 700 1 0 0 in_port_vector.sym`
8			`{`
9			`T 1700 700 5 10 1 1 0 6 1 1`
10			`refdes=btn_pad_in[3:0]`
11			`}`
12			`C 1700 1100 1 0 0 in_port_vector.sym`
13			`{`
14			`T 1700 1100 5 10 1 1 0 6 1 1`
15			`refdes=PosL[7:0]`
16			`}`
17			`C 1700 1500 1 0 0 in_port_vector.sym`
18			`{`
19			`T 1700 1500 5 10 1 1 0 6 1 1`
20			`refdes=PosD[15:0]`
21			`}`
22			`C 1700 1900 1 0 0 in_port.sym`
23			`{`
24			`T 1700 1900 5 10 1 1 0 6 1 1`
25			`refdes=reset`
26			`}`
27			`C 1700 2300 1 0 0 in_port.sym`
28			`{`
29			`T 1700 2300 5 10 1 1 0 6 1 1`
30			`refdes=enable`
31			`}`
32			`C 1700 2700 1 0 0 in_port.sym`
33			`{`
34			`T 1700 2700 5 10 1 1 0 6 1 1`
35			`refdes=clk`
36			`}`
37			`C 4600 300 1 0 0 out_port_vector.sym`
38			`{`
39			`T 5600 300 5 10 1 1 0 0 1 1`
40			`refdes=seg_pad_out[6:0]`
41			`}`
42			`C 4600 700 1 0 0 out_port_vector.sym`
43			`{`
44			`T 5600 700 5 10 1 1 0 0 1 1`
45			`refdes=led_pad_out[7:0]`
46			`}`
47			`C 4600 1100 1 0 0 out_port_vector.sym`
48			`{`
49			`T 5600 1100 5 10 1 1 0 0 1 1`
50			`refdes=an_pad_out[3:0]`
51			`}`
52			`C 4600 1500 1 0 0 out_port_vector.sym`
53			`{`
54			`T 5600 1500 5 10 1 1 0 0 1 1`
55			`refdes=PosS[7:0]`
56			`}`
57			`C 4600 1900 1 0 0 out_port_vector.sym`
58			`{`
59			`T 5600 1900 5 10 1 1 0 0 1 1`
60			`refdes=PosB[3:0]`
61			`}`
62			`C 4600 2300 1 0 0 out_port.sym`
63			`{`
64			`T 5600 2300 5 10 1 1 0 0 1 1`
65			`refdes=dp_pad_out`
66			`}`