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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sch/] [micro_bus_exp5.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2100 300 1 0 0 in_port_vector.sym
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{
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T 2100 300 5 10 1 1 0 6 1 1
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refdes=wdata_in[7:0]
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}
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C 2100 700 1 0 0 in_port_vector.sym
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{
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T 2100 700 5 10 1 1 0 6 1 1
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refdes=mas_4_rdata_in[7:0]
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}
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C 2100 1100 1 0 0 in_port_vector.sym
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{
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T 2100 1100 5 10 1 1 0 6 1 1
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refdes=mas_3_rdata_in[7:0]
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}
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C 2100 1500 1 0 0 in_port_vector.sym
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{
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T 2100 1500 5 10 1 1 0 6 1 1
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refdes=mas_2_rdata_in[7:0]
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}
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C 2100 1900 1 0 0 in_port_vector.sym
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{
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T 2100 1900 5 10 1 1 0 6 1 1
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refdes=mas_1_rdata_in[7:0]
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}
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C 2100 2300 1 0 0 in_port_vector.sym
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{
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T 2100 2300 5 10 1 1 0 6 1 1
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refdes=mas_0_rdata_in[7:0]
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}
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C 2100 2700 1 0 0 in_port_vector.sym
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{
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T 2100 2700 5 10 1 1 0 6 1 1
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refdes=addr_in[7:0]
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}
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C 2100 3100 1 0 0 in_port.sym
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{
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T 2100 3100 5 10 1 1 0 6 1 1
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refdes=wr_in
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}
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C 2100 3500 1 0 0 in_port.sym
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{
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T 2100 3500 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 2100 3900 1 0 0 in_port.sym
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{
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T 2100 3900 5 10 1 1 0 6 1 1
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refdes=rd_in
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}
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C 2100 4300 1 0 0 in_port.sym
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{
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T 2100 4300 5 10 1 1 0 6 1 1
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refdes=enable
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}
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C 2100 4700 1 0 0 in_port.sym
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{
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T 2100 4700 5 10 1 1 0 6 1 1
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refdes=cs_in
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}
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C 2100 5100 1 0 0 in_port.sym
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{
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T 2100 5100 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5400 300  1 0  0 out_port_vector.sym
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{
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T 6400 300 5  10 1 1 0 0 1 1
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refdes=rdata_out[15:0]
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}
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C 5400 700  1 0  0 out_port_vector.sym
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{
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T 6400 700 5  10 1 1 0 0 1 1
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refdes=mas_4_wdata_out[7:0]
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}
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C 5400 1100  1 0  0 out_port_vector.sym
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{
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T 6400 1100 5  10 1 1 0 0 1 1
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refdes=mas_4_addr_out[3:0]
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}
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C 5400 1500  1 0  0 out_port_vector.sym
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{
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T 6400 1500 5  10 1 1 0 0 1 1
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refdes=mas_3_wdata_out[7:0]
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}
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C 5400 1900  1 0  0 out_port_vector.sym
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{
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T 6400 1900 5  10 1 1 0 0 1 1
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refdes=mas_3_addr_out[3:0]
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}
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C 5400 2300  1 0  0 out_port_vector.sym
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{
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T 6400 2300 5  10 1 1 0 0 1 1
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refdes=mas_2_wdata_out[7:0]
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}
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C 5400 2700  1 0  0 out_port_vector.sym
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{
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T 6400 2700 5  10 1 1 0 0 1 1
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refdes=mas_2_addr_out[3:0]
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}
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C 5400 3100  1 0  0 out_port_vector.sym
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{
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T 6400 3100 5  10 1 1 0 0 1 1
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refdes=mas_1_wdata_out[7:0]
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}
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C 5400 3500  1 0  0 out_port_vector.sym
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{
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T 6400 3500 5  10 1 1 0 0 1 1
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refdes=mas_1_addr_out[3:0]
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}
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C 5400 3900  1 0  0 out_port_vector.sym
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{
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T 6400 3900 5  10 1 1 0 0 1 1
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refdes=mas_0_wdata_out[7:0]
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}
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C 5400 4300  1 0  0 out_port_vector.sym
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{
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T 6400 4300 5  10 1 1 0 0 1 1
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refdes=mas_0_addr_out[3:0]
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}
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C 5400 4700  1 0 0 out_port.sym
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{
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T 6400 4700 5  10 1 1 0 0 1 1
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refdes=wait_out
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}
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C 5400 5100  1 0 0 out_port.sym
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{
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T 6400 5100 5  10 1 1 0 0 1 1
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refdes=mas_4_wr_out
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}
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C 5400 5500  1 0 0 out_port.sym
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{
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T 6400 5500 5  10 1 1 0 0 1 1
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refdes=mas_4_rd_out
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}
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C 5400 5900  1 0 0 out_port.sym
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{
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T 6400 5900 5  10 1 1 0 0 1 1
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refdes=mas_4_cs_out
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}
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C 5400 6300  1 0 0 out_port.sym
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{
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T 6400 6300 5  10 1 1 0 0 1 1
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refdes=mas_3_wr_out
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}
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C 5400 6700  1 0 0 out_port.sym
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{
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T 6400 6700 5  10 1 1 0 0 1 1
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refdes=mas_3_rd_out
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}
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C 5400 7100  1 0 0 out_port.sym
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{
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T 6400 7100 5  10 1 1 0 0 1 1
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refdes=mas_3_cs_out
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}
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C 5400 7500  1 0 0 out_port.sym
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{
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T 6400 7500 5  10 1 1 0 0 1 1
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refdes=mas_2_wr_out
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}
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C 5400 7900  1 0 0 out_port.sym
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{
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T 6400 7900 5  10 1 1 0 0 1 1
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refdes=mas_2_rd_out
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}
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C 5400 8300  1 0 0 out_port.sym
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{
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T 6400 8300 5  10 1 1 0 0 1 1
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refdes=mas_2_cs_out
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}
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C 5400 8700  1 0 0 out_port.sym
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{
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T 6400 8700 5  10 1 1 0 0 1 1
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refdes=mas_1_wr_out
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}
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C 5400 9100  1 0 0 out_port.sym
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{
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T 6400 9100 5  10 1 1 0 0 1 1
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refdes=mas_1_rd_out
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}
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C 5400 9500  1 0 0 out_port.sym
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{
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T 6400 9500 5  10 1 1 0 0 1 1
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refdes=mas_1_cs_out
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}
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C 5400 9900  1 0 0 out_port.sym
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{
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T 6400 9900 5  10 1 1 0 0 1 1
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refdes=mas_0_wr_out
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}
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C 5400 10300  1 0 0 out_port.sym
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{
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T 6400 10300 5  10 1 1 0 0 1 1
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refdes=mas_0_rd_out
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}
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C 5400 10700  1 0 0 out_port.sym
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{
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T 6400 10700 5  10 1 1 0 0 1 1
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refdes=mas_0_cs_out
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}

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