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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [doc/] [sym/] [micro_bus_exp9.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  4300 9700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 9850   5 10 1 1 0 0 1 1
4 
device=micro_bus_exp9
5 
T 400 10050 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 10200    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 10200    0 10 0 1 0 0 1 1
10 
library=logic
11 
T 400 10200    0 10 0 1 0 0 1 1
12 
component=micro_bus
13 
T 400 10200    0 10 0 1 0 0 1 1
14 
version=exp9
15 
P 300 200 0 200 10 1 1
16 
{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=wdata_in[7:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=mas_8_rdata_in[7:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=mas_7_rdata_in[7:0]
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 10 1 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=mas_6_rdata_in[7:0]
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pinseq=4
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}
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P 300 1000 0 1000 10 1 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=mas_5_rdata_in[7:0]
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pinseq=5
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}
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P 300 1200 0 1200 10 1 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=mas_4_rdata_in[7:0]
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pinseq=6
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}
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P 300 1400 0 1400 10 1 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=mas_3_rdata_in[7:0]
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pinseq=7
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}
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P 300 1600 0 1600 10 1 1
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{
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T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=mas_2_rdata_in[7:0]
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pinseq=8
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}
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P 300 1800 0 1800 10 1 1
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{
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T 400 1800 5 10 1 1 0 1 1 1
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pinnumber=mas_1_rdata_in[7:0]
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{
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{
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{
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{
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{
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P 300 3000 0 3000 4 0 1
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{
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T 400 3000 5 10 1 1 0 1 1 1
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pinnumber=enable
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{
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{
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{
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{
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T 4500 400 5  10 1 1 0 7 1 1
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{
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T 4500 600 5  10 1 1 0 7 1 1
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{
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{
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T 4500 1000 5  10 1 1 0 7 1 1
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{
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{
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T 4500 1400 5  10 1 1 0 7 1 1
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{
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T 4500 1600 5  10 1 1 0 7 1 1
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{
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T 4500 1800 5  10 1 1 0 7 1 1
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pinnumber=mas_5_addr_out[3:0]
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pinseq=26
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{
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T 4500 2000 5  10 1 1 0 7 1 1
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pinnumber=mas_4_wdata_out[7:0]
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{
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T 4500 2200 5  10 1 1 0 7 1 1
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{
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pinseq=29
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{
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T 4500 2600 5  10 1 1 0 7 1 1
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{
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T 4500 2800 5  10 1 1 0 7 1 1
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pinseq=31
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{
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T 4500 3000 5  10 1 1 0 7 1 1
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{
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T 4500 3200 5  10 1 1 0 7 1 1
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{
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T 4500 3400 5  10 1 1 0 7 1 1
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{
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T 4500 3600 5  10 1 1 0 7 1 1
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{
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T 4500 3800 5  10 1 1 0 7 1 1
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{
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T 4500 4000 5  10 1 1 0 7 1 1
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{
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{
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{
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T 4500 4600 5  10 1 1 0 7 1 1
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{
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T 4500 4800 5  10 1 1 0 7 1 1
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{
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T 4500 5000 5  10 1 1 0 7 1 1
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{
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{
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T 4500 8200 5  10 1 1 0 7 1 1
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