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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
micro_bus
def_lint
 
 
 
 
 
 

 
 
       
 
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="micro_bus"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 

 
 
 
 
 
 
 

 
 
 
   
      fs-lint
 
      
        
        ../verilog/lint/micro_bus_def_lint
        verilogSource
        module
      
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`micro_bus`
40			`def_lint`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50	135	jt_eaton
51	131	jt_eaton
52
53
54	135	jt_eaton
55			`Dut`
56
57
58			`ipxact:library="logic"`
59			`ipxact:name="micro_bus"`
60			`ipxact:version="def_dut.params"/>`
61
62
63	131	jt_eaton
64
65
66
67
68	135	jt_eaton
69			`lint`
70			`:Lint:`
71			`Verilog`
72			`fs-lint`
73
74	131	jt_eaton
75
76
77	135	jt_eaton
78			`rtl_check`
79
80
81			`ipxact:library="Testbench"`
82			`ipxact:name="toolflow"`
83			`ipxact:version="rtl_check"/>`
84
85
86	131	jt_eaton
87	135	jt_eaton
88	131	jt_eaton
89
90
91	135	jt_eaton
92	131	jt_eaton
93
94
95
96
97
98
99	135	jt_eaton
100	131	jt_eaton
101
102
103	135	jt_eaton
104			`fs-lint`
105	131	jt_eaton
106	135	jt_eaton
107
108			`../verilog/lint/micro_bus_def_lint`
109			`verilogSource`
110			`module`
111
112	131	jt_eaton
113
114	135	jt_eaton
115	131	jt_eaton
116
117
118
119
120	135	jt_eaton
121	131	jt_eaton
122
123
124
125
126
127
128	135	jt_eaton
129	131	jt_eaton
130
131
132
133

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_lint.xml] - Blame information for rev 135