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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
micro_bus
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      micro_bus_def_tb
    
  

 
 
 

 
 
 
 
 
 
 
 

 

    addr_width16

 
 
       
 
 
 
              
              Params
              
                
                                   ipxact:library="logic"
                                   ipxact:name="micro_bus"
                                   ipxact:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="micro_bus"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/micro_bus_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
   
      fs-lint
 
 
      
        
        ../verilog/common/micro_bus_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`micro_bus`
40			`def_tb`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`micro_bus_def_tb`
58
59
60
61	131	jt_eaton
62
63
64	135	jt_eaton
65	131	jt_eaton
66
67
68
69
70
71
72
73	135	jt_eaton
74	131	jt_eaton
75	135	jt_eaton
76			`addr_width16`
77
78	131	jt_eaton
79
80	135	jt_eaton
81	131	jt_eaton
82
83
84	135	jt_eaton
85			`Params`
86
87
88			`ipxact:library="logic"`
89			`ipxact:name="micro_bus"`
90			`ipxact:version="def_dut.params"/>`
91
92
93	131	jt_eaton
94	135	jt_eaton
95			`Bfm`
96
97			`ipxact:library="logic"`
98			`ipxact:name="micro_bus"`
99			`ipxact:version="bfm.design"/>`
100
101	131	jt_eaton
102
103	135	jt_eaton
104			`icarus`
105
106
107			`ipxact:library="Testbench"`
108			`ipxact:name="toolflow"`
109			`ipxact:version="icarus"/>`
110
111
112	131	jt_eaton
113
114
115
116
117	135	jt_eaton
118			`common:common:`
119			`Verilog`
120
121
122			`fs-common`
123
124
125	131	jt_eaton
126
127	135	jt_eaton
128			`sim:Simulation:`
129			`Verilog`
130
131
132			`fs-sim`
133
134
135	131	jt_eaton
136
137	135	jt_eaton
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145	131	jt_eaton
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151
152
153
154	135	jt_eaton
155	131	jt_eaton
156
157
158
159
160	135	jt_eaton
161	131	jt_eaton
162	135	jt_eaton
163			`fs-common`
164	131	jt_eaton
165	135	jt_eaton
166
167			`../verilog/tb.ext`
168			`verilogSourcefragment`
169
170	131	jt_eaton
171
172	135	jt_eaton
173	131	jt_eaton
174	135	jt_eaton
175			`fs-sim`
176	131	jt_eaton
177
178	135	jt_eaton
179
180			`../verilog/common/micro_bus_def_tb`
181			`verilogSourcemodule`
182
183	131	jt_eaton
184
185
186	135	jt_eaton
187	131	jt_eaton
188
189
190	135	jt_eaton
191			`fs-lint`
192	131	jt_eaton
193
194	135	jt_eaton
195
196			`../verilog/common/micro_bus_def_tb`
197			`verilogSourcemodule`
198
199	131	jt_eaton
200
201
202	135	jt_eaton
203	131	jt_eaton
204
205
206
207	135	jt_eaton
208	131	jt_eaton
209
210
211
212
213	135	jt_eaton
214	131	jt_eaton
215
216
217
218

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 135