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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_bfm.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
logic
serial_rcvr
bfm.design

 
 

xmit_edge_enable
reg

 
 
 

xmit_parity_enable
reg

 
 

xmit_parity_type
reg

 
 
 

xmit_parity_force
reg

 
 
 

xmit_load
reg

 
 
 

xmit_start_value
reg

 
 

xmit_stop_value
reg

 
 
 
 

xmit_data
reg
WIDTH-10

 
 
 

shift_buffer
wire
WIDTH-10

 
 
 
 
 
 

 
 
 

 

clk


 

reset


 

xmit_edge_enable


 

xmit_parity_enable


 

xmit_parity_type


 

xmit_parity_force


 

xmit_load


 

xmit_start_value


 

xmit_stop_value


 

serial



 

xmit_buffer_empty


 
 
 

xmit_data


 
 
 
 
 
 
 
 
 
 


 

dutx


 8
 4


 
 
 



Line No.	Rev	Author	Line
1	131	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`logic`
17			`serial_rcvr`
18			`bfm.design`
19
20	131	jt_eaton
21
22
23	135	jt_eaton	`xmit_edge_enable`
24			`reg`
25	131	jt_eaton
26
27
28
29
30	135	jt_eaton	`xmit_parity_enable`
31			`reg`
32	131	jt_eaton
33
34
35
36	135	jt_eaton	`xmit_parity_type`
37			`reg`
38	131	jt_eaton
39
40
41
42
43	135	jt_eaton	`xmit_parity_force`
44			`reg`
45	131	jt_eaton
46
47
48
49
50	135	jt_eaton	`xmit_load`
51			`reg`
52	131	jt_eaton
53
54
55
56
57	135	jt_eaton	`xmit_start_value`
58			`reg`
59	131	jt_eaton
60
61
62
63	135	jt_eaton	`xmit_stop_value`
64			`reg`
65	131	jt_eaton
66
67
68
69
70
71	135	jt_eaton	`xmit_data`
72			`reg`
73			`WIDTH-10`
74	131	jt_eaton
75
76
77
78
79	135	jt_eaton	`shift_buffer`
80			`wire`
81			`WIDTH-10`
82	131	jt_eaton
83
84
85
86
87
88
89	135	jt_eaton
90	131	jt_eaton
91
92
93	135	jt_eaton
94	131	jt_eaton
95	135	jt_eaton
96			`clk`
97
98
99	131	jt_eaton
100	135	jt_eaton
101			`reset`
102
103
104	131	jt_eaton
105	135	jt_eaton
106			`xmit_edge_enable`
107
108
109	131	jt_eaton
110	135	jt_eaton
111			`xmit_parity_enable`
112
113
114	131	jt_eaton
115	135	jt_eaton
116			`xmit_parity_type`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`xmit_parity_force`
122
123
124	131	jt_eaton
125	135	jt_eaton
126			`xmit_load`
127
128
129	131	jt_eaton
130	135	jt_eaton
131			`xmit_start_value`
132
133
134	131	jt_eaton
135	135	jt_eaton
136			`xmit_stop_value`
137
138
139	131	jt_eaton
140	135	jt_eaton
141			`serial`
142
143
144
145	131	jt_eaton
146	135	jt_eaton
147			`xmit_buffer_empty`
148
149
150	131	jt_eaton
151
152
153	135	jt_eaton
154			`xmit_data`
155
156
157	131	jt_eaton
158
159
160
161
162
163
164
165
166
167	135	jt_eaton
168
169	131	jt_eaton
170	135	jt_eaton
171			`dutx`
172
173
174			`8`
175			`4`
176
177
178	131	jt_eaton
179
180
181	135	jt_eaton
182

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_bfm.design.xml] - Blame information for rev 135