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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
serial_rcvr
def_lint
 
 
 
 
 

 
 
       
 
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="serial_rcvr"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
 
      
 
 
 

 
 
 
 
  
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/serial_rcvr_def_lint
        verilogSource
        module
      
 
    
 
 
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def_lint`
41	131	jt_eaton
42
43
44
45
46	135	jt_eaton
47	131	jt_eaton
48
49	135	jt_eaton
50	131	jt_eaton
51
52
53	135	jt_eaton
54			`Dut`
55
56
57			`ipxact:library="logic"`
58			`ipxact:name="serial_rcvr"`
59			`ipxact:version="def_dut.params"/>`
60
61
62	131	jt_eaton
63
64
65	135	jt_eaton
66			`lint`
67			`:Lint:`
68			`Verilog`
69			`fs-lint`
70
71	131	jt_eaton
72
73
74	135	jt_eaton
75			`rtl_check`
76
77
78			`ipxact:library="Testbench"`
79			`ipxact:name="toolflow"`
80			`ipxact:version="rtl_check"/>`
81
82
83	131	jt_eaton
84
85	135	jt_eaton
86	131	jt_eaton
87
88
89	135	jt_eaton
90	131	jt_eaton
91
92
93
94	135	jt_eaton
95	131	jt_eaton
96
97
98	135	jt_eaton
99			`fs-lint`
100	131	jt_eaton
101	135	jt_eaton
102
103			`../verilog/lint/serial_rcvr_def_lint`
104			`verilogSource`
105			`module`
106
107	131	jt_eaton
108	135	jt_eaton
109	131	jt_eaton
110
111
112
113
114	135	jt_eaton
115	131	jt_eaton
116
117
118	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_lint.xml] - Blame information for rev 135