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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
serial_rcvr
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      serial_rcvr_def_tb
    
  

 
 
 
 

 
 
 

 
 
 
 
       
 
 
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="serial_rcvr"
                                   ipxact:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="serial_rcvr"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
      
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/serial_rcvr_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/serial_rcvr_def_tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`serial_rcvr_def_tb`
61
62
63
64	131	jt_eaton
65
66
67
68	135	jt_eaton
69	131	jt_eaton
70
71
72	135	jt_eaton
73	131	jt_eaton
74
75
76
77	135	jt_eaton
78	131	jt_eaton
79
80
81	135	jt_eaton
82			`Params`
83
84
85			`ipxact:library="logic"`
86			`ipxact:name="serial_rcvr"`
87			`ipxact:version="def_dut.params"/>`
88
89
90	131	jt_eaton
91	135	jt_eaton
92			`Bfm`
93
94			`ipxact:library="logic"`
95			`ipxact:name="serial_rcvr"`
96			`ipxact:version="bfm.design"/>`
97
98	131	jt_eaton
99
100
101	135	jt_eaton
102			`icarus`
103
104
105			`ipxact:library="Testbench"`
106			`ipxact:name="toolflow"`
107			`ipxact:version="icarus"/>`
108
109
110	131	jt_eaton
111
112
113
114	135	jt_eaton
115			`common:common:`
116			`Verilog`
117
118
119			`fs-common`
120
121
122	131	jt_eaton
123
124	135	jt_eaton
125			`sim:Simulation:`
126			`Verilog`
127
128
129			`fs-sim`
130
131
132	131	jt_eaton
133
134
135	135	jt_eaton
136			`lint:Lint:`
137			`Verilog`
138
139
140			`fs-lint`
141
142
143	131	jt_eaton
144
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151
152	135	jt_eaton
153	131	jt_eaton
154
155
156	135	jt_eaton
157	131	jt_eaton
158	135	jt_eaton
159			`fs-common`
160	131	jt_eaton
161	135	jt_eaton
162
163			`../verilog/top.ext`
164			`verilogSourcefragment`
165
166	131	jt_eaton
167
168	135	jt_eaton
169	131	jt_eaton
170
171	135	jt_eaton
172			`fs-sim`
173	131	jt_eaton
174	135	jt_eaton
175
176			`../verilog/common/serial_rcvr_def_tb`
177			`verilogSourcemodule`
178
179	131	jt_eaton
180
181
182
183	135	jt_eaton
184	131	jt_eaton
185
186
187
188	135	jt_eaton
189			`fs-lint`
190	131	jt_eaton
191	135	jt_eaton
192
193			`../verilog/common/serial_rcvr_def_tb`
194			`verilogSourcemodule`
195
196	131	jt_eaton
197
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200	135	jt_eaton
201	131	jt_eaton
202
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207	135	jt_eaton
208	131	jt_eaton
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216	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_def_tb.xml] - Blame information for rev 135