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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
def
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
          
      
  
 
 
 
 
 
 uart
  
  
      
  
 
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
        
      
 
 
  
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      uart_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_def
    
  

 
 
 
 

 
 
  
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_def
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_def
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 

 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
 
 
  
 
              
              Hierarchical
                  Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`def`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton	`slave_clk`
45
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58
59	131	jt_eaton
60
61	135	jt_eaton	`slave_reset`
62
63
64
65
66
67
68			`reset`
69			`reset`
70
71
72
73
74
75
76	131	jt_eaton
77
78
79
80	135	jt_eaton	`uart`
81
82
83
84
85	131	jt_eaton
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89			`txd_pad_out`
90			`txd_pad_out`
91
92	131	jt_eaton
93
94	135	jt_eaton
95			`rxd_pad_in`
96			`rxd_pad_in`
97
98	131	jt_eaton
99
100	135	jt_eaton
101
102
103
104	131	jt_eaton
105
106	135	jt_eaton
107	131	jt_eaton
108	135	jt_eaton
109	131	jt_eaton
110
111
112
113
114	135	jt_eaton
115	131	jt_eaton
116
117
118	135	jt_eaton
119	131	jt_eaton
120
121
122
123
124	135	jt_eaton
125			`gen_verilog_sim`
126			`104.0`
127			`none`
128			`:Simulation:`
129			`tools/verilog/gen_verilog`
130
131
132			`destination`
133			`uart_def`
134
135
136
137	131	jt_eaton
138
139	135	jt_eaton
140			`gen_verilog_syn`
141			`104.0`
142			`none`
143			`:Synthesis:`
144			`tools/verilog/gen_verilog`
145
146
147			`destination`
148			`uart_def`
149
150
151
152	131	jt_eaton
153
154
155
156	135	jt_eaton
157	131	jt_eaton
158
159	135	jt_eaton
160	131	jt_eaton
161
162
163
164
165	135	jt_eaton
166			`fs-sim`
167	131	jt_eaton
168	135	jt_eaton
169
170			`../verilog/copyright.v`
171			`verilogSourceinclude`
172
173	131	jt_eaton
174
175	135	jt_eaton
176
177			`../verilog/sim/uart_def`
178			`verilogSourcemodule`
179
180	131	jt_eaton
181	135	jt_eaton
182
183			`../verilog/top.body`
184			`verilogSourcefragment`
185
186	131	jt_eaton
187	135	jt_eaton
188
189			`../verilog/top.sim`
190			`verilogSourcefragment`
191
192	131	jt_eaton
193	135	jt_eaton
194			`dest_dir`
195			`../views/sim/`
196			`verilogSourcelibraryDir`
197
198	131	jt_eaton
199
200
201
202
203	135	jt_eaton
204	134	jt_eaton
205
206
207	135	jt_eaton
208			`fs-syn`
209	134	jt_eaton
210	135	jt_eaton
211
212			`../verilog/copyright.v`
213			`verilogSourceinclude`
214
215	131	jt_eaton
216
217	135	jt_eaton
218
219			`../verilog/syn/uart_def`
220			`verilogSourcemodule`
221
222	131	jt_eaton
223	135	jt_eaton
224
225			`../verilog/top.body`
226			`verilogSourcefragment`
227
228	131	jt_eaton
229
230	135	jt_eaton
231			`dest_dir`
232			`../views/syn/`
233			`verilogSourcelibraryDir`
234
235	131	jt_eaton
236
237
238	135	jt_eaton
239	131	jt_eaton
240
241
242	134	jt_eaton
243	131	jt_eaton
244	135	jt_eaton
245	131	jt_eaton
246
247
248
249	135	jt_eaton
250	131	jt_eaton
251
252
253	135	jt_eaton
254
255			`Hierarchical`
256
257
258
259	131	jt_eaton
260
261
262
263
264
265
266	135	jt_eaton
267	131	jt_eaton
268	135	jt_eaton
269			`Hierarchical`
270			`Hierarchical`
271
272	131	jt_eaton
273	135	jt_eaton
274
275			`verilog`
276
277
278			`ipxact:library="Testbench"`
279			`ipxact:name="toolflow"`
280			`ipxact:version="verilog"/>`
281
282
283
284
285
286
287
288
289			`sim:Simulation:`
290	131	jt_eaton
291	135	jt_eaton	`Verilog`
292
293
294			`fs-sim`
295
296
297	131	jt_eaton
298	135	jt_eaton
299			`syn:Synthesis:`
300	131	jt_eaton
301	135	jt_eaton	`Verilog`
302
303
304			`fs-syn`
305
306
307	131	jt_eaton
308
309	135	jt_eaton
310			`doc`
311
312
313			`ipxact:library="Testbench"`
314			`ipxact:name="toolflow"`
315			`ipxact:version="documentation"/>`
316
317			`:Documentation:`
318			`Verilog`
319
320	131	jt_eaton
321
322
323	135	jt_eaton
324	131	jt_eaton
325
326
327
328
329
330
331
332
333	135	jt_eaton
334	131	jt_eaton
335	135	jt_eaton	`parity_enable`
336			`wire`
337			`in`
338
339	131	jt_eaton
340	135	jt_eaton	`divider_in`
341			`wire`
342			`in`
343			`DIV_SIZE-10`
344
345	131	jt_eaton
346	135	jt_eaton	`cts_pad_in`
347			`wire`
348			`in`
349
350	131	jt_eaton
351	135	jt_eaton	`rts_pad_out`
352			`reg`
353			`out`
354
355	131	jt_eaton
356
357	135	jt_eaton	`cts_out`
358			`reg`
359			`out`
360
361	131	jt_eaton
362	135	jt_eaton	`rts_in`
363			`wire`
364			`in`
365
366	131	jt_eaton
367	135	jt_eaton	`txd_parity`
368			`wire`
369			`in`
370
371	131	jt_eaton
372	135	jt_eaton	`txd_force_parity`
373			`wire`
374			`in`
375
376	131	jt_eaton
377	135	jt_eaton	`txd_load`
378			`wire`
379			`in`
380
381	131	jt_eaton
382	135	jt_eaton	`txd_break`
383			`wire`
384			`in`
385
386	131	jt_eaton
387	135	jt_eaton	`txd_data_in`
388			`wire`
389			`in`
390			`SIZE-10`
391
392	131	jt_eaton
393	135	jt_eaton	`txd_buffer_empty`
394			`wire`
395			`out`
396
397	131	jt_eaton
398	135	jt_eaton	`rxd_data_avail_stb`
399			`wire`
400			`in`
401
402	131	jt_eaton
403	135	jt_eaton	`rxd_data_avail`
404			`wire`
405			`out`
406
407	131	jt_eaton
408	135	jt_eaton	`rxd_parity`
409			`wire`
410			`in`
411
412	131	jt_eaton
413	135	jt_eaton	`rxd_force_parity`
414			`wire`
415			`in`
416
417	131	jt_eaton
418	135	jt_eaton	`rxd_data_out`
419			`wire`
420			`out`
421			`SIZE-10`
422
423	131	jt_eaton
424	135	jt_eaton	`rxd_parity_error`
425			`wire`
426			`out`
427
428	131	jt_eaton
429	135	jt_eaton	`rxd_stop_error`
430			`wire`
431			`out`
432
433	131	jt_eaton
434	135	jt_eaton
435	131	jt_eaton
436	135	jt_eaton
437	131	jt_eaton
438
439
440
441
442	135	jt_eaton