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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
rxtx
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
 
        
      
 
 
 
  
 
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
 
        
      
 
  
 
 
 
 
 uart
  
  
      
  
 
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_rxtx
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_rxtx
    
  

 
 
 
 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/uart_rxtx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/uart_rxtx
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
   
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
  
 
 
 
 
 
 

 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
  
 
              
              Hierarchical
                Hierarchical
 
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rxtx.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`rxtx`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59	131	jt_eaton
60
61
62	135	jt_eaton
63	131	jt_eaton
64	135	jt_eaton
65	131	jt_eaton
66
67	135	jt_eaton	`slave_reset`
68
69
70
71
72
73
74			`reset`
75			`reset`
76
77
78
79
80
81	131	jt_eaton
82	135	jt_eaton
83	131	jt_eaton
84	135	jt_eaton
85	131	jt_eaton
86
87	135	jt_eaton	`uart`
88
89
90
91
92	131	jt_eaton
93	135	jt_eaton
94	131	jt_eaton
95	135	jt_eaton
96			`txd_pad_out`
97			`txd_pad_out`
98
99	131	jt_eaton
100
101	135	jt_eaton
102			`rxd_pad_in`
103			`rxd_pad_in`
104
105	131	jt_eaton
106
107	135	jt_eaton
108
109
110
111	131	jt_eaton
112
113	135	jt_eaton
114	131	jt_eaton
115	135	jt_eaton
116	131	jt_eaton
117
118
119
120
121
122
123	135	jt_eaton
124	131	jt_eaton
125
126
127	135	jt_eaton
128	131	jt_eaton
129
130
131
132
133	135	jt_eaton
134			`gen_verilog_sim`
135			`104.0`
136			`none`
137			`:Simulation:`
138			`tools/verilog/gen_verilog`
139
140
141			`destination`
142			`uart_rxtx`
143
144
145
146	131	jt_eaton
147	135	jt_eaton
148			`gen_verilog_syn`
149			`104.0`
150			`none`
151			`:Synthesis:`
152			`tools/verilog/gen_verilog`
153
154
155			`destination`
156			`uart_rxtx`
157
158
159
160	131	jt_eaton
161
162
163
164
165
166	135	jt_eaton
167	131	jt_eaton
168
169
170	135	jt_eaton
171	131	jt_eaton
172	135	jt_eaton
173			`fs-sim`
174	131	jt_eaton
175	135	jt_eaton
176
177			`../verilog/copyright.v`
178			`verilogSourceinclude`
179
180	131	jt_eaton
181
182	135	jt_eaton
183
184			`../verilog/sim/uart_rxtx`
185			`verilogSourcemodule`
186
187	131	jt_eaton
188	135	jt_eaton
189
190			`../verilog/top.body.tx`
191			`verilogSourcefragment`
192
193	131	jt_eaton
194
195	135	jt_eaton
196
197			`../verilog/top.sim`
198			`verilogSourcefragment`
199
200	131	jt_eaton
201	135	jt_eaton
202			`dest_dir`
203			`../views/sim/`
204			`verilogSourcelibraryDir`
205
206	134	jt_eaton
207	131	jt_eaton
208
209
210	135	jt_eaton
211	131	jt_eaton
212
213	135	jt_eaton
214			`fs-syn`
215	131	jt_eaton
216	135	jt_eaton
217
218			`../verilog/copyright.v`
219			`verilogSourceinclude`
220
221	131	jt_eaton
222
223	135	jt_eaton
224
225			`../verilog/syn/uart_rxtx`
226			`verilogSourcemodule`
227
228	134	jt_eaton
229	135	jt_eaton
230
231			`../verilog/top.body.tx`
232			`verilogSourcefragment`
233
234	134	jt_eaton
235	135	jt_eaton
236			`dest_dir`
237			`../views/syn/`
238			`verilogSourcelibraryDir`
239
240	131	jt_eaton
241
242
243	135	jt_eaton
244	131	jt_eaton
245
246
247
248	135	jt_eaton
249	131	jt_eaton
250
251
252
253
254
255	135	jt_eaton
256	131	jt_eaton
257
258	135	jt_eaton
259
260			`Hierarchical`
261
262
263
264	131	jt_eaton
265
266
267	135	jt_eaton
268
269
270
271
272			`Hierarchical`
273			`Hierarchical`
274
275
276
277
278
279			`verilog`
280
281
282			`ipxact:library="Testbench"`
283			`ipxact:name="toolflow"`
284			`ipxact:version="verilog"/>`
285
286
287
288
289
290
291
292
293			`sim:Simulation:`
294	131	jt_eaton
295	135	jt_eaton	`Verilog`
296
297
298			`fs-sim`
299
300
301	131	jt_eaton
302	135	jt_eaton
303			`syn:Synthesis:`
304	131	jt_eaton
305	135	jt_eaton	`Verilog`
306
307
308			`fs-syn`
309
310
311	131	jt_eaton
312
313	135	jt_eaton
314			`doc`
315
316
317			`ipxact:library="Testbench"`
318			`ipxact:name="toolflow"`
319			`ipxact:version="documentation"/>`
320
321			`:Documentation:`
322			`Verilog`
323
324	131	jt_eaton
325
326
327	135	jt_eaton
328	131	jt_eaton
329
330
331
332
333
334
335
336	135	jt_eaton
337	131	jt_eaton
338
339	135	jt_eaton	`parity_enable`
340			`wire`
341			`in`
342
343	131	jt_eaton
344	135	jt_eaton	`divider_in`
345			`wire`
346			`in`
347			`DIV_SIZE-10`
348
349	131	jt_eaton
350	135	jt_eaton	`cts_pad_in`
351			`wire`
352			`in`
353
354	131	jt_eaton
355	135	jt_eaton	`rts_pad_out`
356			`reg`
357			`out`
358
359	131	jt_eaton
360
361	135	jt_eaton	`cts_out`
362			`reg`
363			`out`
364
365	131	jt_eaton
366	135	jt_eaton	`rts_in`
367			`wire`
368			`in`
369
370	131	jt_eaton
371	135	jt_eaton	`txd_parity`
372			`wire`
373			`in`
374
375	131	jt_eaton
376	135	jt_eaton	`txd_force_parity`
377			`wire`
378			`in`
379
380	131	jt_eaton
381	135	jt_eaton	`txd_load`
382			`wire`
383			`in`
384
385	131	jt_eaton
386	135	jt_eaton	`txd_break`
387			`wire`
388			`in`
389
390	131	jt_eaton
391	135	jt_eaton	`txd_data_in`
392			`wire`
393			`in`
394			`SIZE-10`
395
396	131	jt_eaton
397	135	jt_eaton	`txd_buffer_empty`
398			`wire`
399			`out`
400
401	131	jt_eaton
402	135	jt_eaton	`rxd_data_avail_stb`
403			`wire`
404			`in`
405
406	131	jt_eaton
407	135	jt_eaton	`rxd_data_avail`
408			`wire`
409			`out`
410
411	131	jt_eaton
412	135	jt_eaton	`rxd_parity`
413			`wire`
414			`in`
415
416	131	jt_eaton
417	135	jt_eaton	`rxd_force_parity`
418			`wire`
419			`in`
420
421	131	jt_eaton
422	135	jt_eaton	`rxd_data_out`
423			`wire`
424			`out`
425			`SIZE-10`
426
427	131	jt_eaton
428	135	jt_eaton	`rxd_parity_error`
429			`wire`
430			`out`
431
432	131	jt_eaton
433	135	jt_eaton	`rxd_stop_error`
434			`wire`
435			`out`
436
437	131	jt_eaton
438	135	jt_eaton
439	131	jt_eaton
440	135	jt_eaton
441	131	jt_eaton
442
443
444
445	135	jt_eaton