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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
rxtx_tb
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      uart_rxtx_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'hc
    UART_MODEL_SIZE4
    DIVIDER4'b0000

 
 
       
 
 
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="rxtx_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
      
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/uart_rxtx_tb
        verilogSourcemodule
      
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/uart_rxtx_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
  
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`rxtx_tb`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49			`gen_verilog`
50			`104.0`
51			`none`
52			`:common:`
53			`tools/verilog/gen_verilog`
54
55
56			`destination`
57			`uart_rxtx_tb`
58
59
60
61	131	jt_eaton
62
63
64	135	jt_eaton
65	131	jt_eaton
66
67
68	135	jt_eaton
69
70			`UART_MODEL_CLKCNT4'hc`
71			`UART_MODEL_SIZE4`
72			`DIVIDER4'b0000`
73
74	131	jt_eaton
75
76	135	jt_eaton
77	131	jt_eaton
78
79
80	135	jt_eaton
81			`Params`
82
83
84			`ipxact:library="logic"`
85			`ipxact:name="uart"`
86			`ipxact:version="rxtx_dut.params"/>`
87
88
89	131	jt_eaton
90
91	135	jt_eaton
92			`Bfm`
93
94			`ipxact:library="logic"`
95			`ipxact:name="uart"`
96			`ipxact:version="bfm.design"/>`
97
98	131	jt_eaton
99
100
101	135	jt_eaton
102			`icarus`
103
104
105			`ipxact:library="Testbench"`
106			`ipxact:name="toolflow"`
107			`ipxact:version="icarus"/>`
108
109
110	131	jt_eaton
111
112
113
114
115	135	jt_eaton
116			`common:common:`
117			`Verilog`
118
119
120			`fs-common`
121
122
123	131	jt_eaton
124	135	jt_eaton
125			`sim:Simulation:`
126			`Verilog`
127
128
129			`fs-sim`
130
131
132	131	jt_eaton
133
134
135	135	jt_eaton
136			`lint:Lint:`
137			`Verilog`
138
139
140			`fs-lint`
141
142
143	131	jt_eaton
144
145
146	135	jt_eaton
147	131	jt_eaton
148	135	jt_eaton
149	131	jt_eaton
150
151
152
153	135	jt_eaton
154	131	jt_eaton
155	135	jt_eaton
156			`fs-common`
157	131	jt_eaton
158	135	jt_eaton
159
160			`../verilog/tb.ext`
161			`verilogSourcefragment`
162
163	131	jt_eaton
164	135	jt_eaton
165	131	jt_eaton
166
167	135	jt_eaton
168			`fs-sim`
169	131	jt_eaton
170	135	jt_eaton
171
172			`../verilog/common/uart_rxtx_tb`
173			`verilogSourcemodule`
174
175	131	jt_eaton
176	135	jt_eaton
177	131	jt_eaton
178
179
180	135	jt_eaton
181			`fs-lint`
182	131	jt_eaton
183	135	jt_eaton
184
185			`../verilog/common/uart_rxtx_tb`
186			`verilogSourcemodule`
187
188	131	jt_eaton
189	135	jt_eaton
190	131	jt_eaton
191
192
193
194
195	135	jt_eaton
196	131	jt_eaton
197
198	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_tb.xml] - Blame information for rev 135