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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
model
master
 
 
 

 
 
wb
   
  
      
        
     
 
        
         adr
         
         adr
           awidth-10
         
       
 
 
        
         wdata
         
         dout
           dwidth-10
         
       
 
 
        
         rdata
         
         din
           dwidth-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
 
 
 
 
 
     
 
        
  
   
 
 

 

 
 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      model_master
    
  

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
  
    
      destination
      model_master
    
  

 
 
 
 

 
 
 
 
 

 
 
                
                        
                                verilog
                                verilog
                                model_master
                                
                                        
                                                awidth
                                                32
                                        
                                        
                                                dwidth
                                                32
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
 
      
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/sim/master
        verilogSourcefragment
      
 
 
      
        
        ../verilog/sim/master.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/master_copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/model_master
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
    
      fs-syn
 
 
 
 
 
 
 
 
      
        
        ../verilog/sim/master
        verilogSourcefragment
      
 
 
      
        
        ../verilog/sim/master.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/master_copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/model_master
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`model`
40			`master`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton	`wb`
48
49
50
51
52
53	131	jt_eaton
54	135	jt_eaton
55			`adr`
56
57			`adr`
58			`awidth-10`
59
60
61	131	jt_eaton
62
63	135	jt_eaton
64			`wdata`
65
66			`dout`
67			`dwidth-10`
68
69
70	131	jt_eaton
71
72	135	jt_eaton
73			`rdata`
74
75			`din`
76			`dwidth-10`
77
78
79	131	jt_eaton
80
81	135	jt_eaton
82			`sel`
83
84			`sel`
85
86
87	131	jt_eaton
88
89	135	jt_eaton
90			`ack`
91
92			`ack`
93
94
95	131	jt_eaton
96
97	135	jt_eaton
98			`cyc`
99
100			`cyc`
101
102
103	131	jt_eaton
104
105
106	135	jt_eaton
107			`stb`
108
109			`stb`
110
111
112	131	jt_eaton
113
114	135	jt_eaton
115			`we`
116
117			`we`
118
119
120	131	jt_eaton
121
122
123
124
125
126
127	135	jt_eaton
128
129
130
131
132	131	jt_eaton
133
134	135	jt_eaton
135	131	jt_eaton
136	135	jt_eaton
137	131	jt_eaton
138
139
140
141	135	jt_eaton
142	131	jt_eaton
143
144
145
146	135	jt_eaton
147			`gen_verilog_sim`
148			`104.0`
149			`none`
150			`:Simulation:`
151			`tools/verilog/gen_verilog`
152
153
154			`destination`
155			`model_master`
156
157
158
159	131	jt_eaton
160
161
162	135	jt_eaton
163			`gen_verilog_syn`
164			`104.0`
165			`none`
166			`:Synthesis:`
167			`tools/verilog/gen_verilog`
168
169
170			`destination`
171			`model_master`
172
173
174
175	131	jt_eaton
176
177
178
179	135	jt_eaton
180	131	jt_eaton
181
182
183
184
185	135	jt_eaton
186	131	jt_eaton
187
188	135	jt_eaton
189
190			`verilog`
191			`verilog`
192			`model_master`
193
194
195			`awidth`
196			`32`
197
198
199			`dwidth`
200			`32`
201
202
203
204			`fs-sim`
205
206
207
208	131	jt_eaton
209	135	jt_eaton
210	131	jt_eaton
211
212
213	135	jt_eaton
214	131	jt_eaton
215	134	jt_eaton
216	135	jt_eaton
217			`rtl`
218			`verilog:Kactus2:`
219			`verilog`
220
221	134	jt_eaton
222	135	jt_eaton
223
224			`verilog`
225
226
227			`ipxact:library="Testbench"`
228			`ipxact:name="toolflow"`
229			`ipxact:version="verilog"/>`
230
231
232	134	jt_eaton
233
234
235
236	135	jt_eaton
237			`sim:Simulation:`
238			`Verilog`
239
240
241			`fs-sim`
242
243
244	134	jt_eaton
245	135	jt_eaton
246			`syn:Synthesis:`
247			`Verilog`
248
249
250			`fs-syn`
251
252
253	134	jt_eaton
254
255
256
257
258	135	jt_eaton
259			`doc`
260
261
262			`ipxact:library="Testbench"`
263			`ipxact:name="toolflow"`
264			`ipxact:version="documentation"/>`
265
266			`:Documentation:`
267			`Verilog`
268
269	134	jt_eaton
270
271
272
273
274
275	135	jt_eaton
276	134	jt_eaton
277
278
279
280
281
282
283
284	131	jt_eaton
285
286
287	135	jt_eaton
288			`dwidth32`
289			`awidth32`
290
291	131	jt_eaton
292	135	jt_eaton
293	131	jt_eaton
294	135	jt_eaton	`clk`
295			`wire`
296			`in`
297
298	131	jt_eaton
299	135	jt_eaton	`reset`
300			`wire`
301			`in`
302
303	131	jt_eaton
304	135	jt_eaton	`adr`
305			`reg`
306			`out`
307			`awidth-10`
308
309	131	jt_eaton
310
311	135	jt_eaton	`dout`
312			`reg`
313			`out`
314			`dwidth0`
315
316	131	jt_eaton
317
318	135	jt_eaton	`cyc`
319			`reg`
320			`out`
321
322	131	jt_eaton
323	135	jt_eaton	`stb`
324			`reg`
325			`out`
326
327	131	jt_eaton
328	135	jt_eaton	`we`
329			`reg`
330			`out`
331
332	131	jt_eaton
333
334	135	jt_eaton	`sel`
335			`reg`
336			`out`
337			`dwidth/8-10`
338
339	131	jt_eaton
340
341	135	jt_eaton	`din`
342			`wire`
343			`in`
344			`dwidth-10`
345
346	131	jt_eaton
347
348	135	jt_eaton	`ack`
349			`wire`
350			`in`
351
352	131	jt_eaton
353	135	jt_eaton	`err`
354			`wire`
355			`in`
356
357	131	jt_eaton
358	135	jt_eaton	`rty`
359			`wire`
360			`in`
361
362	131	jt_eaton
363
364	135	jt_eaton
365	131	jt_eaton
366	135	jt_eaton
367	131	jt_eaton
368
369
370
371
372	135	jt_eaton
373	134	jt_eaton
374
375	135	jt_eaton
376			`fs-sim`
377	134	jt_eaton
378	135	jt_eaton
379
380			`../verilog/sim/master`
381			`verilogSourcefragment`
382
383	134	jt_eaton
384
385	135	jt_eaton
386
387			`../verilog/sim/master.tasks`
388			`verilogSourcefragment`
389
390	134	jt_eaton
391
392	135	jt_eaton
393
394			`../verilog/master_copyright`
395			`verilogSourceinclude`
396
397	134	jt_eaton
398
399	135	jt_eaton
400
401			`../verilog/sim/model_master`
402			`verilogSourcemodule`
403
404	134	jt_eaton
405
406	135	jt_eaton
407			`dest_dir../views/sim/`
408			`verilogSourcelibraryDir`
409
410	134	jt_eaton
411	135	jt_eaton
412	134	jt_eaton
413
414
415	135	jt_eaton
416			`fs-syn`
417	134	jt_eaton
418
419
420
421
422
423
424
425	135	jt_eaton
426
427			`../verilog/sim/master`
428			`verilogSourcefragment`
429
430	134	jt_eaton
431
432	135	jt_eaton
433
434			`../verilog/sim/master.tasks`
435			`verilogSourcefragment`
436
437	134	jt_eaton
438
439	135	jt_eaton
440
441			`../verilog/master_copyright`
442			`verilogSourceinclude`
443
444	134	jt_eaton
445
446	135	jt_eaton
447
448			`../verilog/sim/model_master`
449			`verilogSourcemodule`
450
451	134	jt_eaton
452
453	135	jt_eaton
454			`dest_dir../views/sim/`
455			`verilogSourcelibraryDir`
456
457	134	jt_eaton
458	135	jt_eaton
459	134	jt_eaton
460
461	135	jt_eaton
462	134	jt_eaton
463
464
465
466
467
468
469	135	jt_eaton
470
471
472