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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_duth.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
wishbone
wb_memory
def_duth.design

 

ack_o



 

adr_i



 

clk_i



 

cyc_i



 

dat_i



 

dat_o



 

rst_i



 

sel_i



 

stb_i



 

we_i



 
 


 

dut


 SRAM_MEM_0_FILE
 SRAM_MEM_1_FILE
 SRAM_MEM_2_FILE
 SRAM_MEM_3_FILE
 adr_width
 dat_width
 mem_size
 wb_addr_width
 wb_byte_lanes
 wb_data_width





Line No.	Rev	Author	Line
1	133	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`wishbone`
17			`wb_memory`
18			`def_duth.design`
19
20	133	jt_eaton
21	135	jt_eaton
22			`ack_o`
23
24
25
26	133	jt_eaton
27	135	jt_eaton
28			`adr_i`
29
30
31
32	133	jt_eaton
33	135	jt_eaton
34			`clk_i`
35
36
37
38	133	jt_eaton
39	135	jt_eaton
40			`cyc_i`
41
42
43
44	133	jt_eaton
45	135	jt_eaton
46			`dat_i`
47
48
49
50	133	jt_eaton
51	135	jt_eaton
52			`dat_o`
53
54
55
56	133	jt_eaton
57	135	jt_eaton
58			`rst_i`
59
60
61
62	133	jt_eaton
63	135	jt_eaton
64			`sel_i`
65
66
67
68	133	jt_eaton
69	135	jt_eaton
70			`stb_i`
71
72
73
74	133	jt_eaton
75	135	jt_eaton
76			`we_i`
77
78
79
80	133	jt_eaton
81
82	135	jt_eaton
83
84	133	jt_eaton
85	135	jt_eaton
86			`dut`
87
88
89			`SRAM_MEM_0_FILE`
90			`SRAM_MEM_1_FILE`
91			`SRAM_MEM_2_FILE`
92			`SRAM_MEM_3_FILE`
93			`adr_width`
94			`dat_width`
95			`mem_size`
96			`wb_addr_width`
97			`wb_byte_lanes`
98			`wb_data_width`
99
100
101
102

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_duth.design.xml] - Blame information for rev 135