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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_memory
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      wb_memory_def_tb
    
  

 
 
 

 
 
 
 

 
 
       
 
 
 
              
              Params
              
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_memory"
                                   ipxact:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_memory"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/common/wb_memory_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
    
      fs-lint
 
 
      
        
        ../verilog/common/wb_memory_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`wb_memory_def_tb`
61
62
63
64	131	jt_eaton
65
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72	135	jt_eaton
73	131	jt_eaton
74
75	135	jt_eaton
76	131	jt_eaton
77
78
79	135	jt_eaton
80			`Params`
81
82
83			`ipxact:library="wishbone"`
84			`ipxact:name="wb_memory"`
85			`ipxact:version="def_dut.params"/>`
86
87
88	131	jt_eaton
89	135	jt_eaton
90			`Bfm`
91
92			`ipxact:library="wishbone"`
93			`ipxact:name="wb_memory"`
94			`ipxact:version="bfm.design"/>`
95
96	131	jt_eaton
97
98
99	135	jt_eaton
100			`icarus`
101
102
103			`ipxact:library="Testbench"`
104			`ipxact:name="toolflow"`
105			`ipxact:version="icarus"/>`
106
107
108	131	jt_eaton
109
110
111
112	135	jt_eaton
113			`common:common:`
114			`Verilog`
115
116
117			`fs-common`
118
119
120	131	jt_eaton
121
122	135	jt_eaton
123			`sim:Simulation:`
124			`Verilog`
125
126
127			`fs-sim`
128
129
130	131	jt_eaton
131	135	jt_eaton
132			`lint:Lint:`
133			`Verilog`
134
135
136			`fs-lint`
137
138
139	131	jt_eaton
140	135	jt_eaton
141	131	jt_eaton
142
143
144
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151	135	jt_eaton
152	131	jt_eaton
153	135	jt_eaton
154			`fs-common`
155	131	jt_eaton
156
157	135	jt_eaton
158
159			`../verilog/tb.ext`
160			`verilogSourcefragment`
161
162	131	jt_eaton
163	135	jt_eaton
164	131	jt_eaton
165
166	135	jt_eaton
167			`fs-sim`
168	131	jt_eaton
169
170	135	jt_eaton
171
172			`../verilog/common/wb_memory_def_tb`
173			`verilogSourcemodule`
174
175	131	jt_eaton
176
177
178	135	jt_eaton
179	131	jt_eaton
180
181
182
183	135	jt_eaton
184			`fs-lint`
185	131	jt_eaton
186
187	135	jt_eaton
188
189			`../verilog/common/wb_memory_def_tb`
190			`verilogSourcemodule`
191
192	131	jt_eaton
193
194	135	jt_eaton
195	131	jt_eaton
196
197
198
199	135	jt_eaton
200	131	jt_eaton
201
202
203
204	135	jt_eaton
205	131	jt_eaton
206

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 135