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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_model/] [rtl/] [xml/] [wb_model_master.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_model
master
 
 
 

 
 
wb
   
  
      
   
 
     
 
        
         adr
         
         adr
           wb_addr_width-10
         
       
 
 
        
         wdata
         
         dout
           wb_data_width-10
         
       
 
 
        
         rdata
         
         din
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
 
 
 
 
 
     
 
 
        
      
   
 

 

 
 
 
 
 
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
  
    
      view
      sim
    

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
  
    
      view
      syn
    

 
 
 
 

 
 
 
 
 

 
 
                
                        
                                verilog
                                verilog
                                wb_model_master
                                
                                        
                                                awidth
                                                32
                                        
                                        
                                                dwidth
                                                32
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
  
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_model/] [rtl/] [xml/] [wb_model_master.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_model`
40			`master`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton	`wb`
48
49
50
51
52	131	jt_eaton
53	135	jt_eaton
54	131	jt_eaton
55	135	jt_eaton
56			`adr`
57
58			`adr`
59			`wb_addr_width-10`
60
61
62	131	jt_eaton
63
64	135	jt_eaton
65			`wdata`
66
67			`dout`
68			`wb_data_width-10`
69
70
71	131	jt_eaton
72
73	135	jt_eaton
74			`rdata`
75
76			`din`
77			`wb_data_width-10`
78
79
80	131	jt_eaton
81
82	135	jt_eaton
83			`sel`
84
85			`sel`
86
87
88	131	jt_eaton
89
90	135	jt_eaton
91			`ack`
92
93			`ack`
94
95
96	131	jt_eaton
97
98	135	jt_eaton
99			`cyc`
100
101			`cyc`
102
103
104	131	jt_eaton
105
106
107	135	jt_eaton
108			`stb`
109
110			`stb`
111
112
113	131	jt_eaton
114
115	135	jt_eaton
116			`we`
117
118			`we`
119
120
121	131	jt_eaton
122
123
124
125
126
127
128	135	jt_eaton
129	131	jt_eaton
130	135	jt_eaton
131
132
133
134	131	jt_eaton
135	135	jt_eaton
136	131	jt_eaton
137	135	jt_eaton
138	131	jt_eaton
139
140
141
142
143
144	135	jt_eaton
145	131	jt_eaton
146	135	jt_eaton
147			`gen_verilogLib_sim`
148			`105.0`
149			`none`
150			`:Simulation:`
151			`tools/verilog/gen_verilogLib`
152
153
154			`dest_dir`
155			`../views`
156
157
158
159			`view`
160			`sim`
161
162
163	131	jt_eaton
164
165	135	jt_eaton
166			`gen_verilogLib_syn`
167			`105.0`
168			`none`
169			`:Synthesis:`
170			`tools/verilog/gen_verilogLib`
171
172
173			`dest_dir`
174			`../views`
175
176
177
178			`view`
179			`syn`
180
181
182	131	jt_eaton
183
184
185
186	135	jt_eaton
187	131	jt_eaton
188
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195	135	jt_eaton
196
197			`verilog`
198			`verilog`
199			`wb_model_master`
200
201
202			`awidth`
203			`32`
204
205
206			`dwidth`
207			`32`
208
209
210
211			`fs-sim`
212
213
214
215	131	jt_eaton
216
217
218	135	jt_eaton
219	131	jt_eaton
220
221	135	jt_eaton
222			`rtl`
223			`verilog:Kactus2:`
224			`verilog`
225
226
227	131	jt_eaton
228	135	jt_eaton
229			`sim:Simulation:`
230
231			`Verilog`
232
233
234			`fs-sim`
235
236
237	131	jt_eaton
238	135	jt_eaton
239			`syn:Synthesis:`
240
241			`Verilog`
242
243
244			`fs-syn`
245
246
247	131	jt_eaton
248
249	135	jt_eaton
250			`doc`
251
252
253			`ipxact:library="Testbench"`
254			`ipxact:name="toolflow"`
255			`ipxact:version="documentation"/>`
256
257			`:Documentation:`
258			`Verilog`
259
260	131	jt_eaton
261	135	jt_eaton
262	131	jt_eaton
263
264
265	135	jt_eaton
266			`dwidth32`
267			`awidth32`
268
269	131	jt_eaton
270	135	jt_eaton
271	131	jt_eaton
272	135	jt_eaton	`clk`
273			`wire`
274			`in`
275
276	131	jt_eaton
277	135	jt_eaton	`reset`
278			`wire`
279			`in`
280
281	131	jt_eaton
282	135	jt_eaton	`adr`
283			`reg`
284			`out`
285			`awidth-10`
286
287	131	jt_eaton
288
289	135	jt_eaton	`dout`
290			`reg`
291			`out`
292			`dwidth0`
293
294	131	jt_eaton
295
296	135	jt_eaton	`cyc`
297			`reg`
298			`out`
299
300	131	jt_eaton
301	135	jt_eaton	`stb`
302			`reg`
303			`out`
304
305	131	jt_eaton
306	135	jt_eaton	`we`
307			`reg`
308			`out`
309
310	131	jt_eaton
311
312	135	jt_eaton	`sel`
313			`reg`
314			`out`
315			`dwidth/8-10`
316
317	131	jt_eaton
318
319	135	jt_eaton	`din`
320			`wire`
321			`in`
322			`dwidth-10`
323
324	131	jt_eaton
325
326	135	jt_eaton	`ack`
327			`wire`
328			`in`
329
330	131	jt_eaton
331	135	jt_eaton	`err`
332			`wire`
333			`in`
334
335	131	jt_eaton
336	135	jt_eaton	`rty`
337			`wire`
338			`in`
339
340	131	jt_eaton
341
342	135	jt_eaton
343	131	jt_eaton
344	135	jt_eaton
345	131	jt_eaton
346
347
348	135	jt_eaton
349	131	jt_eaton
350
351	135	jt_eaton
352			`fs-sim`
353	131	jt_eaton
354	135	jt_eaton
355
356			`../verilog/copyright.v`
357			`verilogSourceinclude`
358
359	131	jt_eaton
360	135	jt_eaton
361
362			`../verilog/top.sim`
363			`verilogSourcemodule`
364
365	131	jt_eaton
366	135	jt_eaton
367	131	jt_eaton
368	135	jt_eaton
369			`fs-syn`
370	131	jt_eaton
371	135	jt_eaton
372
373			`../verilog/copyright.v`
374			`verilogSourceinclude`
375
376	131	jt_eaton
377	135	jt_eaton
378
379			`../verilog/top.syn`
380			`verilogSourcemodule`
381
382	131	jt_eaton
383	135	jt_eaton
384			`dest_dir../views/syn/`
385			`verilogSourcelibraryDir`
386
387	131	jt_eaton
388
389	135	jt_eaton
390	131	jt_eaton
391
392	135	jt_eaton
393	131	jt_eaton
394	135	jt_eaton
395
396
397
398
399
400
401
402