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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bfm.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bfm.design
 
 
 
 

 
 
  
      clk
      
      
      
    
 
  
      reset
      
      
      
    
 
  
      srx_pad_i
      
      
    
 
 
  
      stx_pad_o
      
      
    
 
 
  
      wb_adr_i
      
      
    
 
  
      wb_dat_o
      
      
    
 
  
      wb_dat_i
      
      
    
 
  
      wb_ack_o
      
      
    
 
  
      wb_sel_i
      
      
    
 
  
      wb_stb_i
      
      
    
 
  
      wb_cyc_i
      
      
    
 
  
      wb_we_i
      
      
    
 
 
 
  
      
      
    
 
 

 
 
 

 
 
 
 

i_wb_master 

 WB_DATA_WIDTH
 WB_ADDR_WIDTH


 
 

uart_model 

 UART_MODEL_CLKCNT


 
 

 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bfm.design`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49			`clk`
50
51
52
53
54	131	jt_eaton
55	135	jt_eaton
56			`reset`
57
58
59
60
61	131	jt_eaton
62	135	jt_eaton
63			`srx_pad_i`
64
65
66
67	131	jt_eaton
68
69	135	jt_eaton
70			`stx_pad_o`
71
72
73
74	131	jt_eaton
75
76	135	jt_eaton
77			`wb_adr_i`
78
79
80
81	131	jt_eaton
82	135	jt_eaton
83			`wb_dat_o`
84
85
86
87	131	jt_eaton
88	135	jt_eaton
89			`wb_dat_i`
90
91
92
93	131	jt_eaton
94	135	jt_eaton
95			`wb_ack_o`
96
97
98
99	131	jt_eaton
100	135	jt_eaton
101			`wb_sel_i`
102
103
104
105	131	jt_eaton
106	135	jt_eaton
107			`wb_stb_i`
108
109
110
111	131	jt_eaton
112	135	jt_eaton
113			`wb_cyc_i`
114
115
116
117	131	jt_eaton
118	135	jt_eaton
119			`wb_we_i`
120
121
122
123	131	jt_eaton
124
125
126	135	jt_eaton
127
128
129
130	131	jt_eaton
131
132	135	jt_eaton
133	131	jt_eaton
134
135
136	135	jt_eaton
137	131	jt_eaton
138
139
140
141	135	jt_eaton
142			`i_wb_master`
143
144			`WB_DATA_WIDTH`
145			`WB_ADDR_WIDTH`
146
147
148	131	jt_eaton
149
150	135	jt_eaton
151			`uart_model`
152
153			`UART_MODEL_CLKCNT`
154
155
156	131	jt_eaton
157
158	135	jt_eaton
159	131	jt_eaton
160
161	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bfm.design.xml] - Blame information for rev 135