Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Testbench

clock_gen

def

 master_clk

        clk

        clk

wire

 master_reset

        reset

        reset

reg

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      clock_gen_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      clock_gen_def

                                verilog

                                verilog

                                clock_gen_def

                                                STOP_WIDTH

                                                1

                                                BAD_WIDTH

                                                1

                                        fs-sim

                                rtl

                                verilog:Kactus2:

                                verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

 STOP_WIDTH1

 BAD_WIDTH1

clk

wire

in

reset

reg

out

START

wire

in

STOP

wire

inSTOP_WIDTH-10

BAD

wire

inBAD_WIDTH-10

FAIL

reg

out

FINISH

reg

out

      fs-common

      fs-sim

        ../verilog/clock_gen_sim

        verilogSourcefragment

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/sim/clock_gen_def

        verilogSourcemodule

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

    fs-syn

        ../verilog/clock_gen_syn

        verilogSourcefragment

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/syn/clock_gen_def

        verilogSourcemodule

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir