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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [xml/] [io_host_model_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
io_host_model
def
 
 
 
 
 
 
 

 

  gen_verilog_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      io_host_model_def
    
  

 
 

  gen_verilog_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      io_host_model_def
    
  

 
 

 
 
 
 

       
 
 
 
           
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
io_host_clk
wire
out

 
 
 
io_host_clk_edge
reg
out

 
 
io_host_debug_stats_pcr
reg
out

 
 
 
io_host_in_bits
reg
out
150

 
 
 
io_host_in_ready
wire
in

 
 
io_host_in_valid
reg
out

 
 
io_host_out_bits
wire
in
150

 
 
io_host_out_ready
reg
out

 
 
io_host_out_valid
wire
in

 
 
 

 

 
 
 
 
  
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
 
 
 
      
        
        ../verilog/sim/io_host_model_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
 
      
        
        ../verilog/syn/io_host_model_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
  
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [xml/] [io_host_model_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`io_host_model`
40			`def`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`105.0`
53			`none`
54			`:Simulation:`
55			`tools/verilog/gen_verilog`
56
57
58			`destination`
59			`io_host_model_def`
60
61
62
63
64
65
66			`gen_verilog_syn`
67			`105.0`
68			`none`
69			`:Synthesis:`
70			`tools/verilog/gen_verilog`
71
72
73			`destination`
74			`io_host_model_def`
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91			`verilog`
92
93
94			`ipxact:library="Testbench"`
95			`ipxact:name="toolflow"`
96			`ipxact:version="verilog"/>`
97
98
99
100
101
102
103
104			`sim:Simulation:`
105
106			`Verilog`
107
108
109			`fs-sim`
110
111
112
113
114			`syn:Synthesis:`
115
116			`Verilog`
117
118
119			`fs-syn`
120
121
122
123
124
125			`doc`
126
127
128			`ipxact:library="Testbench"`
129			`ipxact:name="toolflow"`
130			`ipxact:version="documentation"/>`
131
132			`:Documentation:`
133			`Verilog`
134
135
136
137
138
139
140
141
142
143
144
145
146			`clk`
147			`wire`
148			`in`
149
150
151			`reset`
152			`wire`
153			`in`
154
155
156
157
158			`io_host_clk`
159			`wire`
160			`out`
161
162
163
164
165			`io_host_clk_edge`
166			`reg`
167			`out`
168
169
170
171			`io_host_debug_stats_pcr`
172			`reg`
173			`out`
174
175
176
177
178			`io_host_in_bits`
179			`reg`
180			`out`
181			`150`
182
183
184
185
186			`io_host_in_ready`
187			`wire`
188			`in`
189
190
191
192			`io_host_in_valid`
193			`reg`
194			`out`
195
196
197
198			`io_host_out_bits`
199			`wire`
200			`in`
201			`150`
202
203
204
205			`io_host_out_ready`
206			`reg`
207			`out`
208
209
210
211			`io_host_out_valid`
212			`wire`
213			`in`
214
215
216
217
218
219
220
221
222
223
224
225
226
227			`fs-sim`
228
229
230
231			`../verilog/copyright`
232			`verilogSourceinclude`
233
234
235
236
237
238			`../verilog/logic`
239			`verilogSourcefragment`
240
241
242
243
244
245
246
247			`../verilog/sim/io_host_model_def`
248			`verilogSourcemodule`
249
250
251
252
253			`dest_dir../views/sim/`
254			`verilogSourcelibraryDir`
255
256
257
258
259
260
261
262
263			`fs-syn`
264
265
266
267			`../verilog/copyright`
268			`verilogSourceinclude`
269
270
271
272
273
274			`../verilog/logic`
275			`verilogSourcefragment`
276
277
278
279
280
281			`../verilog/syn/io_host_model_def`
282			`verilogSourcemodule`
283
284
285
286
287			`dest_dir../views/syn/`
288			`verilogSourcelibraryDir`
289
290
291
292
293
294
295
296
297
298