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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_mem_model/] [rtl/] [verilog/] [top.sim] - Blame information for rev 135

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1 135 jt_eaton
module micro_bus16_model_def
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#(parameter DELAY    = 15,
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  parameter WIDTH    = 16
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  )
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 (
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  input wire                  clk,
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  input wire                  reset,
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  input  wire [15:0]          rdata,
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  output reg [23:0]           addr,
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  output reg [15:0]           wdata,
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  output reg [1:0]            cs,
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  output reg                  rd,
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  output reg                  wr,
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  output reg                  ub,
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  output reg                  lb
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);
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   reg [15:0]  exp_rdata;
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   reg [15:0]  mask_rdata;
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io_probe_in
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 #(.MESG         ("micro rdata Error"),
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   .WIDTH        (WIDTH),
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   .IN_DELAY     (DELAY)
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  )
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rdata_tpb
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  (
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  .clk            (  clk        ),
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  .expected_value (  exp_rdata  ),
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  .mask           (  mask_rdata ),
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  .signal         (  rdata      )
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  );
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always@(posedge clk)
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  if(reset)
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    begin
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      addr  <= 24'h0000;
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      wdata <=  16'h0000;
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      wr    <=  1'b0;
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      rd    <=  1'b0;
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      cs    <=  2'b00;
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      ub    <=  1'b0;
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      lb    <=  1'b0;
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      exp_rdata    <=  16'h0000;
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      mask_rdata    <=  16'h0000;
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   end
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  // Tasks
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task automatic next;
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  input [31:0] num;
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  repeat (num)       @ (posedge clk);
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endtask // next
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  // idle cycle
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  task u_idle;
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    begin
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      addr  <= 24'h000000;
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      wdata <= 16'h0000;
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      rd    <= 1'b0;
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      cs    <= 2'b00;
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      wr    <= 1'b0;
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      ub    <= 1'b0;
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      lb    <= 1'b0;
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      mask_rdata <= 16'h0000;
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      next(1);
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    end
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  endtask
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  // write cycle
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  task u_write;
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    input [23:0] a;
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    input  [15:0] d;
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    begin
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      $display("%t %m cycle %x %x",$realtime,a,d );
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      addr  <= a;
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      wdata <= d;
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      rd    <= 1'b0;
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      cs    <= 2'b01;
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      wr    <= 1'b1;
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      ub    <= 1'b1;
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      lb    <= 1'b1;
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      next(4);
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      rd    <= 1'b0;
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      cs    <= 2'b00;
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      wr    <= 1'b0;
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      ub    <= 1'b0;
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      lb    <= 1'b0;
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      next(1);
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    end
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  endtask
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  // read cycle
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  task u_read;
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    input   [23:0]  a;
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    output  [15:0]   d;
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     begin
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      addr  <= a;
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      wdata <= 16'h0000;
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      rd    <= 1'b1;
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      cs    <= 2'b01;
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      wr    <= 1'b0;
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      ub    <= 1'b1;
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      lb    <= 1'b1;
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      next(4);
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      d     <= rdata;
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      $display("%t %m  cycle %x %x",$realtime,a,rdata );
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      rd    <= 1'b1;
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      next(1);
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      rd    <= 1'b0;
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      ub    <= 1'b0;
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      lb    <= 1'b0;
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      cs    <= 2'b00;
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      next(1);
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    end
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  endtask
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  // Compare cycle (read data from location and compare with expected data)
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  task u_cmp;
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    input  [23:0] a;
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    input  [15:0] d_exp;
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     begin
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      addr      <= a;
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      wdata     <= 16'h0000;
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      rd        <= 1'b1;
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      ub        <= 1'b1;
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      lb        <= 1'b1;
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      cs        <= 2'b01;
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      wr        <= 1'b0;
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      exp_rdata <= d_exp;
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      next(5);
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      mask_rdata  <= 16'hffff;
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      next(1);
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      $display("%t %m   cycle %x %x",$realtime,a,d_exp );
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      mask_rdata <= 16'h0000;
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      rd         <= 1'b0;
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      ub         <= 1'b0;
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      lb         <= 1'b0;
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      cs         <= 2'b00;
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      next(1);
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   end
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  endtask
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endmodule
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