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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
micro_bus_model
def
 
 
 
 

 
 
mb
  
 
 
 
  
      
  
 
 
    
 
 
      
        addr
        
        addr
          addr_width-10
        
      
 
      
        wdata
        
        wdata
          70
        
      
 
      
        rd
        
        rd
        
      
 
 
      
        wr
        
        wr
        
      
 
 
      
        cs
        
        cs
        
      
 
 
 
    
 
 
        
      
 
 
  
 
  
 
 

 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      micro_bus_model_def
    
  

 
 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      micro_bus_model_def
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
      
        
        ../verilog/sim/micro_bus_model_def
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcefragment
      
 
      
        
        ../verilog/syn/micro_bus_model_def
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
  
 
 
 
 

 
        
                        
                                Hierarchical
                                
                        
                
 
 
 
 
  
 
              
              Hierarchical
                     Hierarchical
 
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

 
addr_width
16
 
OUT_DELAY
15
 
 
OUT_WIDTH
10
 

 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
addr
reg
out
150

 
wdata
reg
out
70

 
rd
reg
out

 
wr
reg
out

 
rdata
wire
inout
70

 
 
cs
reg
out

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [micro_bus_model/] [rtl/] [xml/] [micro_bus_model_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`micro_bus_model`
40			`def`
41	131	jt_eaton
42
43
44
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton	`mb`
49
50	131	jt_eaton
51
52
53	135	jt_eaton
54
55
56	131	jt_eaton
57
58	135	jt_eaton
59	131	jt_eaton
60
61	135	jt_eaton
62			`addr`
63
64			`addr`
65			`addr_width-10`
66
67
68	131	jt_eaton
69	135	jt_eaton
70			`wdata`
71
72			`wdata`
73			`70`
74
75
76	131	jt_eaton
77	135	jt_eaton
78			`rd`
79
80			`rd`
81
82
83	131	jt_eaton
84
85	135	jt_eaton
86			`wr`
87
88			`wr`
89
90
91	131	jt_eaton
92
93	135	jt_eaton
94			`cs`
95
96			`cs`
97
98
99	131	jt_eaton
100
101	133	jt_eaton
102	135	jt_eaton
103	133	jt_eaton
104	135	jt_eaton
105
106
107	133	jt_eaton
108
109	135	jt_eaton
110	133	jt_eaton
111	135	jt_eaton
112	133	jt_eaton
113	131	jt_eaton
114	135	jt_eaton
115	131	jt_eaton
116	135	jt_eaton
117	131	jt_eaton
118	135	jt_eaton
119			`gen_verilog_sim`
120			`104.0`
121			`none`
122			`:Simulation:`
123			`tools/verilog/gen_verilog`
124
125
126			`destination`
127			`micro_bus_model_def`
128
129
130
131	131	jt_eaton
132
133
134	133	jt_eaton
135	135	jt_eaton
136			`gen_verilog_syn`
137			`104.0`
138			`none`
139			`:Synthesis:`
140			`tools/verilog/gen_verilog`
141
142
143			`destination`
144			`micro_bus_model_def`
145
146
147
148	131	jt_eaton
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154	135	jt_eaton
155	131	jt_eaton
156	135	jt_eaton
157			`fs-sim`
158	131	jt_eaton
159	135	jt_eaton
160
161			`../verilog/copyright.v`
162			`verilogSourceinclude`
163
164	131	jt_eaton
165	135	jt_eaton
166
167			`../verilog/top.sim`
168			`verilogSourcefragment`
169
170	131	jt_eaton
171	135	jt_eaton
172
173			`../verilog/sim/micro_bus_model_def`
174			`verilogSourcemodule`
175
176	131	jt_eaton
177	135	jt_eaton
178			`dest_dir../views/sim/`
179			`verilogSourcelibraryDir`
180
181	133	jt_eaton
182	131	jt_eaton
183	133	jt_eaton
184
185
186	135	jt_eaton
187	131	jt_eaton
188
189	135	jt_eaton
190			`fs-syn`
191	131	jt_eaton
192	135	jt_eaton
193
194			`../verilog/copyright.v`
195			`verilogSourceinclude`
196
197	131	jt_eaton
198	135	jt_eaton
199
200			`../verilog/top.syn`
201			`verilogSourcefragment`
202
203	131	jt_eaton
204	135	jt_eaton
205
206			`../verilog/syn/micro_bus_model_def`
207			`verilogSourcemodule`
208
209	131	jt_eaton
210
211
212
213	135	jt_eaton
214			`dest_dir../views/syn/`
215			`verilogSourcelibraryDir`
216
217	131	jt_eaton
218	135	jt_eaton
219	134	jt_eaton
220
221
222	135	jt_eaton
223	134	jt_eaton
224
225
226
227	135	jt_eaton
228	134	jt_eaton
229	135	jt_eaton
230
231			`Hierarchical`
232
233
234
235
236
237
238
239
240
241
242			`Hierarchical`
243			`Hierarchical`
244
245
246
247
248			`verilog`
249
250
251			`ipxact:library="Testbench"`
252			`ipxact:name="toolflow"`
253			`ipxact:version="verilog"/>`
254
255
256
257
258
259
260
261
262
263
264
265			`sim:Simulation:`
266	131	jt_eaton
267	135	jt_eaton	`Verilog`
268
269
270			`fs-sim`
271
272
273	131	jt_eaton
274	135	jt_eaton
275			`syn:Synthesis:`
276	131	jt_eaton
277	135	jt_eaton	`Verilog`
278
279
280			`fs-syn`
281
282
283	131	jt_eaton
284
285	135	jt_eaton
286			`doc`
287
288
289			`ipxact:library="Testbench"`
290			`ipxact:name="toolflow"`
291			`ipxact:version="documentation"/>`
292
293			`:Documentation:`
294			`Verilog`
295
296	131	jt_eaton
297	135	jt_eaton
298	131	jt_eaton
299
300
301	135	jt_eaton
302	131	jt_eaton
303	135	jt_eaton	`addr_width`
304			`16`
305	131	jt_eaton
306	135	jt_eaton	`OUT_DELAY`
307			`15`
308	131	jt_eaton
309
310	135	jt_eaton	`OUT_WIDTH`
311			`10`
312	131	jt_eaton
313	135	jt_eaton
314	131	jt_eaton
315
316
317
318
319	135	jt_eaton
320	131	jt_eaton
321	135	jt_eaton	`clk`
322			`wire`
323			`in`
324
325	131	jt_eaton
326	135	jt_eaton	`reset`
327			`wire`
328			`in`
329
330	131	jt_eaton
331	135	jt_eaton	`addr`
332			`reg`
333			`out`
334			`150`
335
336	131	jt_eaton
337	135	jt_eaton	`wdata`
338			`reg`
339			`out`
340			`70`
341
342	131	jt_eaton
343	135	jt_eaton	`rd`
344			`reg`
345			`out`
346
347	131	jt_eaton
348	135	jt_eaton	`wr`
349			`reg`
350			`out`
351
352	131	jt_eaton
353	135	jt_eaton	`rdata`
354			`wire`
355			`inout`
356			`70`
357
358	131	jt_eaton
359
360	135	jt_eaton	`cs`
361			`reg`
362			`out`
363
364	131	jt_eaton
365	135	jt_eaton
366	131	jt_eaton
367	135	jt_eaton
368	131	jt_eaton
369
370
371
372
373
374
375
376
377
378
379
380
381
382	135	jt_eaton