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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [xml/] [or1200_dbg_model_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
or1200_dbg_model
def
 
 
 
 
 
 
 
 debug
   
 
  
      
   
 
 
 
    
 
        
         addr
         
         dbg_adr_i
           310
           reg
         
       
 
 
        
         wdata
         
         dbg_dat_i
           310
           reg
         
       
 
 
        
         rdata
         
         dbg_dat_o
           310
         
       
 
 
        
         lss
         
         dbg_lss_o
           30
         
       
 
 
        
         is
         
         dbg_is_o
           10
         
       
 
 
        
         wp
         
         dbg_wp_o
           100
         
       
 
 
 
 
      
        stall
        dbg_stall_i
           reg
           
      
 
 
      
        ewt
        dbg_ewt_i
           reg
         
      
 
 
      
        bp
        dbg_bp_o
       
      
 
 
      
        stb
        dbg_stb_i
           reg

      
 
 
      
        we
        dbg_we_i
           reg

      
 
 
      
        ack
        dbg_ack_o
      
 
 
    
 
 
        
      
 
 
 
 
  
 
  
 
 
 
 
 
 
 
 
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.task
        verilogSourcefragment
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
  
 
 
 
 

       
 
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

OUT_WIDTH10

 

 
clk
wire
in

 
reset
wire
in

 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [or1200_dbg_model/] [rtl/] [xml/] [or1200_dbg_model_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`or1200_dbg_model`
40			`def`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45
46
47
48	135	jt_eaton	`debug`
49
50	131	jt_eaton
51	135	jt_eaton
52
53
54	131	jt_eaton
55
56
57	135	jt_eaton
58	131	jt_eaton
59	135	jt_eaton
60			`addr`
61
62			`dbg_adr_i`
63			`310`
64			`reg`
65
66
67	131	jt_eaton
68
69	135	jt_eaton
70			`wdata`
71
72			`dbg_dat_i`
73			`310`
74			`reg`
75
76
77	131	jt_eaton
78
79	135	jt_eaton
80			`rdata`
81
82			`dbg_dat_o`
83			`310`
84
85
86	131	jt_eaton
87
88	135	jt_eaton
89			`lss`
90
91			`dbg_lss_o`
92			`30`
93
94
95	131	jt_eaton
96
97	135	jt_eaton
98			`is`
99
100			`dbg_is_o`
101			`10`
102
103
104	131	jt_eaton
105
106	135	jt_eaton
107			`wp`
108
109			`dbg_wp_o`
110			`100`
111
112
113	131	jt_eaton
114
115
116
117	135	jt_eaton
118			`stall`
119			`dbg_stall_i`
120			`reg`
121
122
123	131	jt_eaton
124
125	135	jt_eaton
126			`ewt`
127			`dbg_ewt_i`
128			`reg`
129
130
131	131	jt_eaton
132
133	135	jt_eaton
134			`bp`
135			`dbg_bp_o`
136
137
138	131	jt_eaton
139
140	135	jt_eaton
141			`stb`
142			`dbg_stb_i`
143			`reg`
144
145
146	131	jt_eaton
147
148	135	jt_eaton
149			`we`
150			`dbg_we_i`
151			`reg`
152
153
154	131	jt_eaton
155
156	135	jt_eaton
157			`ack`
158			`dbg_ack_o`
159
160	131	jt_eaton
161
162	135	jt_eaton
163	131	jt_eaton
164	135	jt_eaton
165
166
167	131	jt_eaton
168
169
170
171	135	jt_eaton
172	131	jt_eaton
173	135	jt_eaton
174	131	jt_eaton
175
176	135	jt_eaton
177	131	jt_eaton
178
179
180
181
182
183
184	135	jt_eaton
185	131	jt_eaton
186
187	135	jt_eaton
188			`gen_verilog_sim`
189			`104.0`
190			`none`
191			`:Simulation:`
192			`tools/verilog/gen_verilog`
193
194
195			`destination`
196			`top.out.sim`
197
198
199			`dest_dir`
200			`../verilog`
201
202
203
204	131	jt_eaton
205
206	135	jt_eaton
207			`gen_verilog_syn`
208			`104.0`
209			`none`
210			`:Synthesis:`
211			`tools/verilog/gen_verilog`
212
213
214			`destination`
215			`top.out.syn`
216
217
218			`dest_dir`
219			`../verilog`
220
221
222
223	131	jt_eaton
224
225
226	135	jt_eaton
227			`gen_verilogLib_sim`
228			`105.0`
229			`none`
230			`:Simulation:`
231			`tools/verilog/gen_verilogLib`
232
233
234			`dest_dir`
235			`../views`
236
237
238			`view`
239			`sim`
240
241
242
243	131	jt_eaton
244
245	135	jt_eaton
246			`gen_verilogLib_syn`
247			`105.0`
248			`none`
249			`:Synthesis:`
250			`tools/verilog/gen_verilogLib`
251
252
253			`dest_dir`
254			`../views`
255
256
257			`view`
258			`syn`
259
260
261
262	131	jt_eaton
263
264	135	jt_eaton
265	131	jt_eaton
266
267
268	135	jt_eaton
269	131	jt_eaton
270	135	jt_eaton
271			`fs-sim`
272	131	jt_eaton
273	135	jt_eaton
274
275			`../verilog/copyright.v`
276			`verilogSourceinclude`
277
278	131	jt_eaton
279	135	jt_eaton
280
281			`../verilog/sim/top.out.sim`
282			`verilogSourcemodule`
283
284	131	jt_eaton
285
286	135	jt_eaton
287
288			`../verilog/top.task`
289			`verilogSourcefragment`
290
291	131	jt_eaton
292
293
294	135	jt_eaton
295			`dest_dir../views/sim/`
296			`verilogSourcelibraryDir`
297
298	131	jt_eaton
299
300
301
302
303	135	jt_eaton
304	131	jt_eaton
305
306	135	jt_eaton
307			`fs-syn`
308	131	jt_eaton
309	135	jt_eaton
310
311			`../verilog/copyright.v`
312			`verilogSourceinclude`
313
314	131	jt_eaton
315	135	jt_eaton
316
317			`../verilog/syn/top.out.syn`
318			`verilogSourcemodule`
319
320	131	jt_eaton
321	135	jt_eaton
322			`dest_dir../views/syn/`
323			`verilogSourcelibraryDir`
324
325	131	jt_eaton
326	135	jt_eaton
327	131	jt_eaton
328
329
330	135	jt_eaton
331	131	jt_eaton
332	135	jt_eaton
333
334
335
336
337
338
339
340
341
342
343
344
345			`sim:Simulation:`
346	131	jt_eaton
347	135	jt_eaton	`Verilog`
348
349
350			`fs-sim`
351
352
353	131	jt_eaton
354	135	jt_eaton
355			`syn:Synthesis:`
356	131	jt_eaton
357	135	jt_eaton	`Verilog`
358
359
360			`fs-syn`
361
362
363	131	jt_eaton
364
365	135	jt_eaton
366			`doc`
367
368
369			`ipxact:library="Testbench"`
370			`ipxact:name="toolflow"`
371			`ipxact:version="documentation"/>`
372
373			`:Documentation:`
374			`Verilog`
375
376	131	jt_eaton
377	135	jt_eaton
378	131	jt_eaton
379
380
381	135	jt_eaton
382			`OUT_WIDTH10`
383
384	131	jt_eaton
385	135	jt_eaton
386	131	jt_eaton
387	135	jt_eaton	`clk`
388			`wire`
389			`in`
390
391	131	jt_eaton
392	135	jt_eaton	`reset`
393			`wire`
394			`in`
395
396	131	jt_eaton
397
398	135	jt_eaton
399	131	jt_eaton
400	135	jt_eaton
401	131	jt_eaton
402
403
404
405
406
407
408
409
410
411
412
413
414
415	135	jt_eaton