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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [verilog/] [tasks] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton
task automatic next;
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  input [31:0] num;
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  repeat (num)       @ (posedge clk);
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endtask
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task clear_rx_host;
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 begin
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 rx_clr               <= 1'b1;
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 next(1);
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 rx_clr               <= 1'b0;
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 end
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endtask
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task send_byte;
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  input [7:0] byte_out;
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   begin
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   $display("%t %m %2h",$realtime ,byte_out  );
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   tx_data  <= byte_out;
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   next(1);
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   tx_write   <= 1'b1;
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   next(1);
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   tx_write   <= 1'b0;
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   next(1);
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   while(busy)   next(1);
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   mask_tx_ack_err <= 1'b1;
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   next(1);
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   mask_tx_ack_err <= 1'b0;
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   end
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endtask // send_byte
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task rcv_byte;
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  input [7:0] byte_in;
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   begin
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   exp_rcv_byte  <= byte_in;
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   while(!rx_read)  next(1);
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   $display("%t           checking    %h",$realtime,byte_in);
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   mask_rcv_byte <= 8'hff;
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   next(1);
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   mask_rcv_byte <= 8'h00;
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end
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endtask
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