OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sym/] [uart_host_def.sym] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  3900 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
3 
T 400 2250   5 10 1 1 0 0 1 1
4 
device=uart_host_def
5 
T 400 2450 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 2600    0 10 0 1 0 0 1 1
8 
vendor=opencores.org
9 
T 400 2600    0 10 0 1 0 0 1 1
10 
library=Testbench
11 
T 400 2600    0 10 0 1 0 0 1 1
12 
component=uart_host
13 
T 400 2600    0 10 0 1 0 0 1 1
14 
version=def
15 
P 300 200 0 200 10 1 1
16 
{
17 
T 400 200 5 10 1 1 0 1 1 1
18 
pinnumber=rxd_data_out[7:0]
19 
T 400 200 5 10 0 1 0 1 1 1
20 
pinseq=1
21 
}
22 
P 300 400 0 400 4 0 1
23 
{
24 
T 400 400 5 10 1 1 0 1 1 1
25 
pinnumber=txd_buffer_empty
26 
T 400 400 5 10 0 1 0 1 1 1
27 
pinseq=2
28 
}
29 
P 300 600 0 600 4 0 1
30 
{
31 
T 400 600 5 10 1 1 0 1 1 1
32 
pinnumber=rxd_stop_error
33 
T 400 600 5 10 0 1 0 1 1 1
34 
pinseq=3
35 
}
36 
P 300 800 0 800 4 0 1
37 
{
38 
T 400 800 5 10 1 1 0 1 1 1
39 
pinnumber=rxd_parity_error
40 
T 400 800 5 10 0 1 0 1 1 1
41 
pinseq=4
42 
}
43 
P 300 1000 0 1000 4 0 1
44 
{
45 
T 400 1000 5 10 1 1 0 1 1 1
46 
pinnumber=rxd_data_avail
47 
T 400 1000 5 10 0 1 0 1 1 1
48 
pinseq=5
49 
}
50 
P 300 1200 0 1200 4 0 1
51 
{
52 
T 400 1200 5 10 1 1 0 1 1 1
53 
pinnumber=reset
54 
T 400 1200 5 10 0 1 0 1 1 1
55 
pinseq=6
56 
}
57 
P 300 1400 0 1400 4 0 1
58 
{
59 
T 400 1400 5 10 1 1 0 1 1 1
60 
pinnumber=clk
61 
T 400 1400 5 10 0 1 0 1 1 1
62 
pinseq=7
63 
}
64 
P 4200 200 4500 200 10 1 1
65 
{
66 
T 4100 200 5  10 1 1 0 7 1 1
67 
pinnumber=txd_data_in[7:0]
68 
T 4100 200 5  10 0 1 0 7 1 1
69 
pinseq=8
70 
}
71 
P 4200 400 4500 400 4 0 1
72 
{
73 
T 4100 400 5  10 1 1 0 7 1 1
74 
pinnumber=txd_parity
75 
T 4200 400 5  10 0 1 0 7 1 1
76 
pinseq=9
77 
}
78 
P 4200 600 4500 600 4 0 1
79 
{
80 
T 4100 600 5  10 1 1 0 7 1 1
81 
pinnumber=txd_load
82 
T 4200 600 5  10 0 1 0 7 1 1
83 
pinseq=10
84 
}
85 
P 4200 800 4500 800 4 0 1
86 
{
87 
T 4100 800 5  10 1 1 0 7 1 1
88 
pinnumber=txd_force_parity
89 
T 4200 800 5  10 0 1 0 7 1 1
90 
pinseq=11
91 
}
92 
P 4200 1000 4500 1000 4 0 1
93 
{
94 
T 4100 1000 5  10 1 1 0 7 1 1
95 
pinnumber=txd_break
96 
T 4200 1000 5  10 0 1 0 7 1 1
97 
pinseq=12
98 
}
99 
P 4200 1200 4500 1200 4 0 1
100 
{
101 
T 4100 1200 5  10 1 1 0 7 1 1
102 
pinnumber=rxd_parity
103 
T 4200 1200 5  10 0 1 0 7 1 1
104 
pinseq=13
105 
}
106 
P 4200 1400 4500 1400 4 0 1
107 
{
108 
T 4100 1400 5  10 1 1 0 7 1 1
109 
pinnumber=rxd_force_parity
110 
T 4200 1400 5  10 0 1 0 7 1 1
111 
pinseq=14
112 
}
113 
P 4200 1600 4500 1600 4 0 1
114 
{
115 
T 4100 1600 5  10 1 1 0 7 1 1
116 
pinnumber=rxd_data_avail_stb
117 
T 4200 1600 5  10 0 1 0 7 1 1
118 
pinseq=15
119 
}
120 
P 4200 1800 4500 1800 4 0 1
121 
{
122 
T 4100 1800 5  10 1 1 0 7 1 1
123 
pinnumber=parity_enable
124 
T 4200 1800 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.