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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
toolflow
icarus
 

 
 

  gen_elab_filelists
  104.0
  none
  
    :*Simulation:*
    :*Synthesis:*
  
  tools/sys/gen_elab_child_filelist
  
    
      top_file
      ./TestBench
    
    
      top
    
  

 
 

  gen_filelists
  104.0
  none
  
    :*Simulation:*
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
  
    
      top_file
      ./TestBench
    
    
      top
    
  

 
 
 
 

  gen_cov_filelist
  104.0
  none
  
    :*Lint:*
  
  tools/sys/gen_child_filelist
  
    
      top_file
      "-v ./TestBench"
    
    
      top
    
    
      suffix
      COV
    
    
      leader
      "-v "
    
  

 
 
 
 
 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  tools/verilog/gen_verilogLib
    
    
      view
      lint
    
  

 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 
 

 
 
 
 
 
 

 
     
        PERIOD40
        TIMEOUT100000
      
 
 
                
                        
                                Bfm
                                
                        
                
 
 
 
       
 
 
              
              Bfm
              Bfm
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 
 
 

 
clk
  wire
  in

 
START
  wire
  in

 
 
FAIL
  wire
  out

 
 
 
FINISH
  wire
  out

 
 

 

 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`toolflow`
40			`icarus`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45	135	jt_eaton
46			`gen_elab_filelists`
47			`104.0`
48			`none`
49
50	134	jt_eaton	`:Simulation:`
51			`:Synthesis:`
52	135	jt_eaton
53			`tools/sys/gen_elab_child_filelist`
54
55
56			`top_file`
57			`./TestBench`
58
59
60			`top`
61
62
63
64	134	jt_eaton
65
66	135	jt_eaton
67			`gen_filelists`
68			`104.0`
69			`none`
70
71	131	jt_eaton	`:Simulation:`
72			`:Synthesis:`
73	135	jt_eaton
74			`tools/sys/gen_child_filelist`
75
76
77			`top_file`
78			`./TestBench`
79
80
81			`top`
82
83
84
85	131	jt_eaton
86
87	134	jt_eaton
88
89	135	jt_eaton
90			`gen_cov_filelist`
91			`104.0`
92			`none`
93
94	131	jt_eaton	`:Lint:`
95	135	jt_eaton
96			`tools/sys/gen_child_filelist`
97
98
99			`top_file`
100			`"-v ./TestBench"`
101
102
103			`top`
104
105
106			`suffix`
107			`COV`
108
109
110			`leader`
111			`"-v "`
112
113
114
115	131	jt_eaton
116
117
118
119
120
121
122
123	135	jt_eaton
124			`gen_verilogLib_sim`
125			`105.0`
126			`none`
127			`:Simulation:`
128			`tools/verilog/gen_verilogLib`
129
130
131			`view`
132			`sim`
133
134
135
136	131	jt_eaton
137
138	135	jt_eaton
139			`gen_verilogLib_syn`
140			`105.0`
141			`none`
142			`:Synthesis:`
143			`tools/verilog/gen_verilogLib`
144
145
146			`view`
147			`syn`
148
149
150
151	131	jt_eaton
152
153	135	jt_eaton
154			`gen_verilogLib_lint`
155			`105.0`
156			`none`
157			`:Lint:`
158			`tools/verilog/gen_verilogLib`
159
160
161			`view`
162			`lint`
163
164
165
166	131	jt_eaton
167	135	jt_eaton
168	131	jt_eaton
169
170
171	135	jt_eaton
172	131	jt_eaton
173
174
175
176
177	135	jt_eaton
178			`fs-sim`
179	131	jt_eaton
180	135	jt_eaton
181			`dest_dir`
182			`../views/sim/`
183			`verilogSource`
184			`libraryDir`
185
186	131	jt_eaton
187	135	jt_eaton
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193			`fs-syn`
194	131	jt_eaton
195	135	jt_eaton
196			`dest_dir`
197			`../views/syn/`
198			`verilogSource`
199			`libraryDir`
200
201	131	jt_eaton
202	135	jt_eaton
203	131	jt_eaton
204
205
206	135	jt_eaton
207			`fs-lint`
208	131	jt_eaton
209	135	jt_eaton
210			`dest_dir`
211			`../views/lint/`
212			`verilogSource`
213			`libraryDir`
214
215	131	jt_eaton
216	135	jt_eaton
217	131	jt_eaton
218
219
220
221
222
223
224	135	jt_eaton
225
226
227
228
229	131	jt_eaton
230
231	135	jt_eaton
232	131	jt_eaton
233	135	jt_eaton
234			`PERIOD40`
235			`TIMEOUT100000`
236
237	131	jt_eaton
238
239	135	jt_eaton
240
241			`Bfm`
242
243
244
245	131	jt_eaton
246	135	jt_eaton
247	131	jt_eaton
248	135	jt_eaton
249	131	jt_eaton
250
251	135	jt_eaton
252			`Bfm`
253			`Bfm`
254
255	131	jt_eaton
256
257	135	jt_eaton
258			`sim`
259			`:Simulation:`
260			`Verilog`
261
262			`fs-sim`
263
264	131	jt_eaton
265
266	135	jt_eaton
267			`syn`
268			`:Synthesis:`
269			`Verilog`
270
271			`fs-syn`
272
273	131	jt_eaton
274
275
276	135	jt_eaton
277			`lint`
278			`:Lint:`
279			`Verilog`
280
281			`fs-lint`
282
283	131	jt_eaton
284
285
286
287	135	jt_eaton
288	131	jt_eaton
289
290
291
292
293
294
295
296
297
298
299
300
301	135	jt_eaton
302	131	jt_eaton
303	135	jt_eaton	`clk`
304			`wire`
305			`in`
306
307	131	jt_eaton
308	135	jt_eaton	`START`
309			`wire`
310			`in`
311
312	131	jt_eaton
313
314	135	jt_eaton	`FAIL`
315			`wire`
316			`out`
317
318	131	jt_eaton
319
320
321	135	jt_eaton	`FINISH`
322			`wire`
323			`out`
324
325	131	jt_eaton
326
327	135	jt_eaton
328	131	jt_eaton
329	135	jt_eaton
330	131	jt_eaton
331	135	jt_eaton
332	131	jt_eaton
333
334	135	jt_eaton
335	131	jt_eaton
336
337