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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ise.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
toolflow
ise
 

 
 
 
 
 

  gen_ise_filelist
  104.0
  none
  
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
  
    
      top
    
    
      suffix
      ISE
    
    
      leader
      "verilog work "
    
    
      overlay_src_ven
      opencores.org
    
    
      overlay_src_lib
      cde
    
    
      overlay_des_ven
      digilentinc.com
    
    
      overlay_des_lib
      Nexys2
    
 
  

 
 
 
 
 
 
 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 

 

 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 

 
 

 
       
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
      
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`toolflow`
40			`ise`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45
46
47
48	135	jt_eaton
49			`gen_ise_filelist`
50			`104.0`
51			`none`
52
53			`:Synthesis:`
54
55			`tools/sys/gen_child_filelist`
56
57
58			`top`
59
60
61			`suffix`
62			`ISE`
63
64
65			`leader`
66			`"verilog work "`
67
68
69			`overlay_src_ven`
70			`opencores.org`
71
72
73			`overlay_src_lib`
74			`cde`
75
76
77			`overlay_des_ven`
78			`digilentinc.com`
79
80
81			`overlay_des_lib`
82			`Nexys2`
83
84	131	jt_eaton
85	135	jt_eaton
86
87	131	jt_eaton
88
89
90
91
92
93
94
95	135	jt_eaton
96
97			`gen_verilogLib_syn`
98			`105.0`
99			`none`
100			`:Synthesis:`
101			`tools/verilog/gen_verilogLib`
102
103
104			`view`
105			`syn`
106
107
108
109	131	jt_eaton
110	135	jt_eaton
111
112
113
114
115			`fs-syn`
116
117
118			`dest_dir`
119			`../views/syn/`
120			`verilogSource`
121			`libraryDir`
122
123
124
125
126
127
128
129
130
131
132
133			`syn`
134			`:Synthesis:`
135			`Verilog`
136
137			`fs-syn`
138
139
140
141
142
143
144
145
146
147	131	jt_eaton
148
149

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ise.xml] - Blame information for rev 135