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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_testmux.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
clock
testmux
 
 
 

 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
sel
wire
in

 
clk_0
wire
in

 
clk_1
wire
in

 
 
 
clk_out
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`clock`
15			`testmux`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21
22
23
24
25	135	jt_eaton
26	131	jt_eaton
27
28
29	135	jt_eaton
30	131	jt_eaton
31	135	jt_eaton
32			`fs-sim`
33	131	jt_eaton
34
35	135	jt_eaton
36			`dest_dir`
37			`../verilog/`
38			`verilogSourcelibraryDir`
39
40	131	jt_eaton
41	135	jt_eaton
42	131	jt_eaton
43
44	135	jt_eaton
45			`fs-syn`
46	131	jt_eaton
47	135	jt_eaton
48			`dest_dir`
49			`../verilog/`
50			`verilogSourcelibraryDir`
51
52	131	jt_eaton
53
54
55	135	jt_eaton
56	131	jt_eaton
57
58	135	jt_eaton
59	131	jt_eaton
60	135	jt_eaton	`fs-lint`
61
62			`dest_dir`
63			`../verilog/`
64			`verilogSourcelibraryDir`
65
66	131	jt_eaton
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72
73	135	jt_eaton
74	131	jt_eaton
75
76
77
78
79
80
81	135	jt_eaton
82
83	131	jt_eaton
84
85	135	jt_eaton
86			`sim:Simulation:`
87			`Verilog`
88
89
90			`fs-sim`
91
92
93	131	jt_eaton
94	135	jt_eaton
95			`syn:Synthesis:`
96			`Verilog`
97
98
99			`fs-syn`
100
101
102	131	jt_eaton
103
104	135	jt_eaton
105			`doc`
106
107
108			`ipxact:library="Testbench"`
109			`ipxact:name="toolflow"`
110			`ipxact:version="documentation"/>`
111
112			`:Documentation:`
113			`Verilog`
114
115	131	jt_eaton
116
117
118
119	135	jt_eaton
120	131	jt_eaton
121
122
123
124	135	jt_eaton
125	131	jt_eaton
126	135	jt_eaton	`sel`
127			`wire`
128			`in`
129
130	131	jt_eaton
131	135	jt_eaton	`clk_0`
132			`wire`
133			`in`
134
135	131	jt_eaton
136	135	jt_eaton	`clk_1`
137			`wire`
138			`in`
139
140	131	jt_eaton
141
142
143	135	jt_eaton	`clk_out`
144			`wire`
145			`out`
146
147	131	jt_eaton
148
149
150
151
152	135	jt_eaton
153	131	jt_eaton
154	135	jt_eaton
155	131	jt_eaton
156
157
158
159
160
161
162
163
164
165
166
167
168	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_testmux.xml] - Blame information for rev 135