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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [busDef/] [xml/] [jtag_rpc_classic_rtl.abstractionDefinition.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
cde
jtag
rpc_classic_rtl
 

  
 
 
 
    
      shiftcapture_dr_clk
      The clock input coordinates all activities for the internal logic within the jtag bus
      
        
          true
        
        
          CLOCK
          optional
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
        true
      
    
 
 
    
      update_dr_clk
      The clock input coordinates all activities for the internal logic within the jtag bus
      
        
          true
        
        
          CLOCK
          optional
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
        true
      
    
 
 
    
      test_logic_reset
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          optional
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
       true
      
    
 
 
    
      run_test
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
    
      select
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
    
      shift_dr
      
        
          CLOCK
          illegal
        
        
          ENABLE
          optional
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
 
 
    
      capture_dr
      
        
          CLOCK
          illegal
        
        
          ENABLE
          optional
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
    
      tdi
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          out
        
        
          optional
          1
          in
        
      
    
 
 
 
 
 
    
      tdo
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          optional
          1
          in
        
        
          optional
          1
          out
        
      
    
 
 
 
 
 
 
  

 
 
 
 
 
 
 
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [busDef/] [xml/] [jtag_rpc_classic_rtl.abstractionDefinition.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31	135	jt_eaton
32			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
33	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
34			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
35	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
36			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
37	131	jt_eaton
38
39	135	jt_eaton	`opencores.org`
40			`cde`
41			`jtag`
42			`rpc_classic_rtl`
43	131	jt_eaton
44	135	jt_eaton
45
46	131	jt_eaton
47
48
49	135	jt_eaton
50			`shiftcapture_dr_clk`
51			`The clock input coordinates all activities for the internal logic within the jtag bus`
52
53
54			`true`
55
56
57			`CLOCK`
58			`optional`
59
60
61			`ENABLE`
62			`illegal`
63
64
65			`RESET`
66			`illegal`
67
68
69			`optional`
70			`1`
71			`out`
72
73
74			`optional`
75			`1`
76			`in`
77
78			`true`
79
80
81	131	jt_eaton
82
83	135	jt_eaton
84			`update_dr_clk`
85			`The clock input coordinates all activities for the internal logic within the jtag bus`
86
87
88			`true`
89
90
91			`CLOCK`
92			`optional`
93
94
95			`ENABLE`
96			`illegal`
97
98
99			`RESET`
100			`illegal`
101
102
103			`optional`
104			`1`
105			`out`
106
107
108			`optional`
109			`1`
110			`in`
111
112			`true`
113
114
115	131	jt_eaton
116
117	135	jt_eaton
118			`test_logic_reset`
119
120
121			`CLOCK`
122			`illegal`
123
124
125			`ENABLE`
126			`illegal`
127
128
129			`RESET`
130			`optional`
131
132
133			`optional`
134			`1`
135			`out`
136
137
138			`optional`
139			`1`
140			`in`
141
142			`true`
143
144
145	131	jt_eaton
146
147	135	jt_eaton
148			`run_test`
149
150
151			`CLOCK`
152			`illegal`
153
154
155			`ENABLE`
156			`illegal`
157
158
159			`RESET`
160			`illegal`
161
162
163			`optional`
164			`1`
165			`out`
166
167
168			`optional`
169			`1`
170			`in`
171
172
173
174	131	jt_eaton
175
176
177	135	jt_eaton
178			`select`
179
180
181			`CLOCK`
182			`illegal`
183
184
185			`ENABLE`
186			`illegal`
187
188
189			`RESET`
190			`illegal`
191
192
193			`optional`
194			`1`
195			`out`
196
197
198			`optional`
199			`1`
200			`in`
201
202
203
204	131	jt_eaton
205
206
207	135	jt_eaton
208			`shift_dr`
209
210
211			`CLOCK`
212			`illegal`
213
214
215			`ENABLE`
216			`optional`
217
218
219			`RESET`
220			`illegal`
221
222
223			`optional`
224			`1`
225			`out`
226
227
228			`optional`
229			`1`
230			`in`
231
232
233
234	131	jt_eaton
235
236
237
238
239	135	jt_eaton
240			`capture_dr`
241
242
243			`CLOCK`
244			`illegal`
245
246
247			`ENABLE`
248			`optional`
249
250
251			`RESET`
252			`illegal`
253
254
255			`optional`
256			`1`
257			`out`
258
259
260			`optional`
261			`1`
262			`in`
263
264
265
266	131	jt_eaton
267
268
269	135	jt_eaton
270			`tdi`
271
272
273			`CLOCK`
274			`illegal`
275
276
277			`ENABLE`
278			`illegal`
279
280
281			`RESET`
282			`illegal`
283
284
285			`optional`
286			`1`
287			`out`
288
289
290			`optional`
291			`1`
292			`in`
293
294
295
296	131	jt_eaton
297
298
299
300
301	135	jt_eaton
302			`tdo`
303
304
305			`CLOCK`
306			`illegal`
307
308
309			`ENABLE`
310			`illegal`
311
312
313			`RESET`
314			`illegal`
315
316
317			`optional`
318			`1`
319			`in`
320
321
322			`optional`
323			`1`
324			`out`
325
326
327
328	131	jt_eaton
329
330
331
332
333
334	135	jt_eaton
335
336	131	jt_eaton
337
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344