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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sch/] [cde_jtag_classic_rpc_reg.sch] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton	`v 20100214 1`
2	135	jt_eaton	`C 2500 300 1 0 0 in_port_vector.sym`
3	131	jt_eaton	`{`
4			`T 2500 300 5 10 1 1 0 6 1 1`
5			`refdes=capture_value[BITS-1:0]`
6			`}`
7			`C 2500 700 1 0 0 in_port.sym`
8			`{`
9			`T 2500 700 5 10 1 1 0 6 1 1`
10			`refdes=update_dr_clk`
11			`}`
12			`C 2500 1100 1 0 0 in_port.sym`
13			`{`
14			`T 2500 1100 5 10 1 1 0 6 1 1`
15			`refdes=test_logic_reset`
16			`}`
17			`C 2500 1500 1 0 0 in_port.sym`
18			`{`
19			`T 2500 1500 5 10 1 1 0 6 1 1`
20			`refdes=tdi`
21			`}`
22			`C 2500 1900 1 0 0 in_port.sym`
23			`{`
24			`T 2500 1900 5 10 1 1 0 6 1 1`
25			`refdes=shiftcapture_dr_clk`
26			`}`
27			`C 2500 2300 1 0 0 in_port.sym`
28			`{`
29			`T 2500 2300 5 10 1 1 0 6 1 1`
30			`refdes=shift_dr`
31			`}`
32			`C 2500 2700 1 0 0 in_port.sym`
33			`{`
34			`T 2500 2700 5 10 1 1 0 6 1 1`
35			`refdes=select`
36			`}`
37			`C 2500 3100 1 0 0 in_port.sym`
38			`{`
39			`T 2500 3100 5 10 1 1 0 6 1 1`
40			`refdes=capture_dr`
41			`}`
42	135	jt_eaton	`C 6000 300 1 0 0 out_port_vector.sym`
43	131	jt_eaton	`{`
44			`T 7000 300 5 10 1 1 0 0 1 1`
45			`refdes=update_value[BITS-1:0]`
46			`}`
47			`C 6000 700 1 0 0 out_port.sym`
48			`{`
49			`T 7000 700 5 10 1 1 0 0 1 1`
50			`refdes=tdo`
51			`}`