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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_cmd_sync.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
classic_cmd_sync
 
 

 
 jtag
 
 
 
  
      
 
 
 
 
    
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
 
        
      
 
 
            
        tdi
        tdi
 
        
      
 
 
                  
        tdo
        tdo
 
        
      
 
 
 
 
 
 
    
 
      
      
 
 
 
  
 
  
 
 

 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_cmd_sync
    
  

 
 
 
 

 
 
 
 

       
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 
reset
wire
in

 
 
syn_capture_dr
reg
out

 
 
syn_update_dr
reg
out

 
 
 
test_logic_reset
wire
in

 
 
capture_dr
wire
in

 
 
shift_dr
wire
in

 
 
update_dr_clk
wire
in

 
 
 
select
wire
in

 
 
 
shiftcapture_dr_clk
wire
in

 
 
 
tdi
wire
in

 
 
 
tdo
wire
out

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/classic_cmd_sync
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
   
      fs-sim
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_classic_cmd_sync
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_classic_cmd_sync
        verilogSourcemodule
      
 
 
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_cmd_sync.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`jtag`
15			`classic_cmd_sync`
16
17
18
19
20			`jtag`
21
22
23
24
25
26
27
28
29
30
31
32
33			`test_logic_reset`
34			`test_logic_reset`
35
36
37
38			`capture_dr`
39			`capture_dr`
40
41
42
43			`shift_dr`
44			`shift_dr`
45
46
47
48			`update_dr_clk`
49			`update_dr_clk`
50
51
52
53
54			`select`
55			`select`
56
57
58
59
60			`shiftcapture_dr_clk`
61			`shiftcapture_dr_clk`
62
63
64
65
66
67
68			`tdi`
69			`tdi`
70
71
72
73
74
75
76			`tdo`
77			`tdo`
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110			`gen_verilog`
111			`104.0`
112			`none`
113			`:common:`
114			`tools/verilog/gen_verilog`
115
116
117			`destination`
118			`jtag_classic_cmd_sync`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136			`verilog`
137
138
139			`ipxact:library="Testbench"`
140			`ipxact:name="toolflow"`
141			`ipxact:version="verilog"/>`
142
143
144
145
146
147
148			`common:common:`
149			`Verilog`
150
151
152			`fs-common`
153
154
155
156
157
158
159
160			`sim:Simulation:`
161			`Verilog`
162
163
164			`fs-sim`
165
166
167
168
169			`syn:Synthesis:`
170			`Verilog`
171
172
173			`fs-syn`
174
175
176
177
178
179
180			`doc`
181
182
183			`ipxact:library="Testbench"`
184			`ipxact:name="toolflow"`
185			`ipxact:version="documentation"/>`
186
187			`:Documentation:`
188			`Verilog`
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204			`clk`
205			`wire`
206			`in`
207
208
209
210			`reset`
211			`wire`
212			`in`
213
214
215
216			`syn_capture_dr`
217			`reg`
218			`out`
219
220
221
222			`syn_update_dr`
223			`reg`
224			`out`
225
226
227
228
229			`test_logic_reset`
230			`wire`
231			`in`
232
233
234
235			`capture_dr`
236			`wire`
237			`in`
238
239
240
241			`shift_dr`
242			`wire`
243			`in`
244
245
246
247			`update_dr_clk`
248			`wire`
249			`in`
250
251
252
253
254			`select`
255			`wire`
256			`in`
257
258
259
260
261			`shiftcapture_dr_clk`
262			`wire`
263			`in`
264
265
266
267
268			`tdi`
269			`wire`
270			`in`
271
272
273
274
275			`tdo`
276			`wire`
277			`out`
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299			`fs-common`
300
301
302
303			`../verilog/classic_cmd_sync`
304			`verilogSourcefragment`
305
306
307
308
309
310
311
312
313
314
315
316
317			`fs-sim`
318
319
320
321			`../verilog/copyright`
322			`verilogSourceinclude`
323
324
325
326
327
328			`../verilog/common/jtag_classic_cmd_sync`
329			`verilogSourcemodule`
330
331
332
333
334			`dest_dir`
335			`../views/sim/`
336			`verilogSource`
337			`libraryDir`
338
339
340
341
342
343
344			`fs-syn`
345
346
347
348
349			`../verilog/copyright`
350			`verilogSourceinclude`
351
352
353
354
355
356			`../verilog/common/jtag_classic_cmd_sync`
357			`verilogSourcemodule`
358
359
360
361
362
363
364
365
366			`dest_dir`
367			`../views/syn/`
368			`verilogSource`
369			`libraryDir`
370
371
372
373
374
375
376
377
378
379			`fs-lint`
380
381			`dest_dir`
382			`../views/syn/`
383			`verilogSource`
384			`libraryDir`
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399