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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_sync.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
jtag
classic_sync
 
 

 
 
 jtag
 
  
      
 
 
 
 
    
 
      
        test_logic_reset
        test_logic_reset
      
 
      
        capture_dr
        capture_dr
      
 
      
        shift_dr
        shift_dr
      
 
      
        update_dr_clk
        update_dr_clk
      
 
 
      
        tdi
        tdi
      
 
      
        tdo
        tdo
 
      
      
 
      
        select
        select
      
 
 
      
        shiftcapture_dr_clk
        shiftcapture_dr_clk
 
        
      
 
 
 
    
 
 
        
      
 
 
  
 
  
 
 
 syn_jtag
 
 
 
 
  
      
 
 
 
 
    
 
 
 
      
        clk
        syn_clk
      
 
 
      
        test_logic_reset
        syn_reset
      
 
      
        capture_dr
        syn_capture_dr
      
 
      
        shift_dr
        syn_shift_dr
      
 
      
        update_dr
        syn_update_dr
      
 
 
      
        tdi
        syn_tdi_o
  
      
 
      
        tdo
        syn_tdo_i
 
     
      
 
      
        select
        syn_select
      
 
 
 
    
 
      
      
 
 
 
 
  
 
  
 

 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_classic_sync
    
  

 
 
 
 

 
 
 
 

       
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
      
 
 
 
 
 

 
clk
wire
in

 
 
syn_reset
reg
out

 
 
syn_shift_dr
reg
out

 
 
syn_capture_dr
reg
out

 
 
syn_update_dr
reg
out

 
syn_tdi_o
reg
out

 
syn_tdo_i
wire
in

 
 
syn_clk
wire
out

 
syn_select
reg
out

 
 
test_logic_reset
wire
in

 
capture_dr
wire
in

 
shift_dr
wire
in

 
update_dr_clk
wire
in

 
 
tdi
wire
in

 
 
tdo
wire
out

 
 
select
wire
in

 
shiftcapture_dr_clk
wire
in

 
 
 

 

 
 
 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/classic_sync
        verilogSourcefragment
      
 
 
 
 
 
   
 
 
 
 
   
      fs-sim
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_classic_sync
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/jtag_classic_sync
        verilogSourcemodule
      
 
 
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_sync.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`jtag`
15			`classic_sync`
16	131	jt_eaton
17
18	135	jt_eaton
19	131	jt_eaton
20
21	135	jt_eaton	`jtag`
22
23
24
25
26	131	jt_eaton
27
28	135	jt_eaton
29
30	131	jt_eaton
31	135	jt_eaton
32			`test_logic_reset`
33			`test_logic_reset`
34
35	131	jt_eaton
36	135	jt_eaton
37			`capture_dr`
38			`capture_dr`
39
40	131	jt_eaton
41	135	jt_eaton
42			`shift_dr`
43			`shift_dr`
44
45	131	jt_eaton
46	135	jt_eaton
47			`update_dr_clk`
48			`update_dr_clk`
49
50	131	jt_eaton
51
52	135	jt_eaton
53			`tdi`
54			`tdi`
55
56	131	jt_eaton
57	135	jt_eaton
58			`tdo`
59			`tdo`
60
61
62
63	131	jt_eaton
64	135	jt_eaton
65			`select`
66			`select`
67
68	131	jt_eaton
69
70	135	jt_eaton
71			`shiftcapture_dr_clk`
72			`shiftcapture_dr_clk`
73
74
75
76	131	jt_eaton
77
78
79	135	jt_eaton
80	131	jt_eaton
81
82	135	jt_eaton
83
84	131	jt_eaton
85
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89	131	jt_eaton
90
91	135	jt_eaton	`syn_jtag`
92
93	131	jt_eaton
94
95
96	135	jt_eaton
97
98
99	131	jt_eaton
100
101
102	135	jt_eaton
103	131	jt_eaton
104
105
106	135	jt_eaton
107			`clk`
108			`syn_clk`
109
110	131	jt_eaton
111
112	135	jt_eaton
113			`test_logic_reset`
114			`syn_reset`
115
116	131	jt_eaton
117	135	jt_eaton
118			`capture_dr`
119			`syn_capture_dr`
120
121	131	jt_eaton
122	135	jt_eaton
123			`shift_dr`
124			`syn_shift_dr`
125
126	131	jt_eaton
127	135	jt_eaton
128			`update_dr`
129			`syn_update_dr`
130
131	134	jt_eaton
132
133	135	jt_eaton
134			`tdi`
135			`syn_tdi_o`
136
137
138	134	jt_eaton
139	135	jt_eaton
140			`tdo`
141			`syn_tdo_i`
142
143
144
145	134	jt_eaton
146	135	jt_eaton
147			`select`
148			`syn_select`
149
150	134	jt_eaton
151
152
153	135	jt_eaton
154	134	jt_eaton
155	135	jt_eaton
156
157	134	jt_eaton
158
159	135	jt_eaton
160	134	jt_eaton
161	135	jt_eaton
162	131	jt_eaton
163	135	jt_eaton
164	131	jt_eaton
165	135	jt_eaton
166	134	jt_eaton
167
168
169
170	135	jt_eaton
171	134	jt_eaton
172
173
174	131	jt_eaton
175	135	jt_eaton
176			`gen_verilog`
177			`104.0`
178			`none`
179			`:common:`
180			`tools/verilog/gen_verilog`
181
182
183			`destination`
184			`jtag_classic_sync`
185
186
187
188	131	jt_eaton
189
190
191
192	135	jt_eaton
193	131	jt_eaton
194
195
196
197	135	jt_eaton
198
199	131	jt_eaton
200
201	135	jt_eaton
202			`verilog`
203
204
205			`ipxact:library="Testbench"`
206			`ipxact:name="toolflow"`
207			`ipxact:version="verilog"/>`
208
209
210	131	jt_eaton
211
212
213	135	jt_eaton
214			`common:common:`
215			`Verilog`
216
217
218			`fs-common`
219
220
221	133	jt_eaton
222	131	jt_eaton
223
224
225	135	jt_eaton
226			`sim:Simulation:`
227			`Verilog`
228
229
230			`fs-sim`
231
232
233	134	jt_eaton
234	135	jt_eaton
235			`syn:Synthesis:`
236			`Verilog`
237
238
239			`fs-syn`
240
241
242	134	jt_eaton
243
244
245	135	jt_eaton
246			`doc`
247
248
249			`ipxact:library="Testbench"`
250			`ipxact:name="toolflow"`
251			`ipxact:version="documentation"/>`
252
253			`:Documentation:`
254			`Verilog`
255
256	134	jt_eaton
257
258
259
260
261	131	jt_eaton
262	135	jt_eaton
263	131	jt_eaton
264
265
266
267
268	135	jt_eaton
269	131	jt_eaton
270	135	jt_eaton	`clk`
271			`wire`
272			`in`
273
274	131	jt_eaton
275
276	135	jt_eaton	`syn_reset`
277			`reg`
278			`out`
279
280	131	jt_eaton
281	134	jt_eaton
282	135	jt_eaton	`syn_shift_dr`
283			`reg`
284			`out`
285
286	134	jt_eaton
287
288	135	jt_eaton	`syn_capture_dr`
289			`reg`
290			`out`
291
292	134	jt_eaton
293
294	135	jt_eaton	`syn_update_dr`
295			`reg`
296			`out`
297
298	134	jt_eaton
299	135	jt_eaton	`syn_tdi_o`
300			`reg`
301			`out`
302
303	134	jt_eaton
304	135	jt_eaton	`syn_tdo_i`
305			`wire`
306			`in`
307
308	134	jt_eaton
309
310	135	jt_eaton	`syn_clk`
311			`wire`
312			`out`
313
314	134	jt_eaton
315	135	jt_eaton	`syn_select`
316			`reg`
317			`out`
318
319	131	jt_eaton
320	134	jt_eaton
321	135	jt_eaton	`test_logic_reset`
322			`wire`
323			`in`
324
325	134	jt_eaton
326	135	jt_eaton	`capture_dr`
327			`wire`
328			`in`
329
330	134	jt_eaton
331	135	jt_eaton	`shift_dr`
332			`wire`
333			`in`
334
335	134	jt_eaton
336	135	jt_eaton	`update_dr_clk`
337			`wire`
338			`in`
339
340	131	jt_eaton
341
342	135	jt_eaton	`tdi`
343			`wire`
344			`in`
345
346	131	jt_eaton
347
348	135	jt_eaton	`tdo`
349			`wire`
350			`out`
351
352	134	jt_eaton
353
354	135	jt_eaton	`select`
355			`wire`
356			`in`
357
358	134	jt_eaton
359	135	jt_eaton	`shiftcapture_dr_clk`
360			`wire`
361			`in`
362
363	134	jt_eaton
364
365
366	135	jt_eaton
367	134	jt_eaton
368	135	jt_eaton
369	134	jt_eaton
370
371	131	jt_eaton
372
373
374
375
376
377	135	jt_eaton
378	131	jt_eaton
379	135	jt_eaton
380			`fs-common`
381	131	jt_eaton
382	135	jt_eaton
383
384			`../verilog/classic_sync`
385			`verilogSourcefragment`
386
387	131	jt_eaton
388
389
390
391
392	135	jt_eaton
393	131	jt_eaton
394
395
396
397	135	jt_eaton
398			`fs-sim`
399
400
401
402			`../verilog/copyright`
403			`verilogSourceinclude`
404
405
406
407
408
409			`../verilog/common/jtag_classic_sync`
410			`verilogSourcemodule`
411
412
413
414
415			`dest_dir`
416			`../views/sim/`
417			`verilogSource`
418			`libraryDir`
419
420
421
422
423
424
425			`fs-syn`
426
427
428
429
430			`../verilog/copyright`
431			`verilogSourceinclude`
432
433
434
435
436
437			`../verilog/common/jtag_classic_sync`
438			`verilogSourcemodule`
439
440
441
442
443
444
445
446
447			`dest_dir`
448			`../views/syn/`
449			`verilogSource`
450			`libraryDir`
451
452
453
454
455
456
457
458
459
460			`fs-lint`
461
462			`dest_dir`
463			`../views/syn/`
464			`verilogSource`
465			`libraryDir`
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480